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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Subject: [PATCH v2 2/3] target/arm: Fix sve_access_check for SME
Date: Sun, 22 Jun 2025 14:35:08 -0700	[thread overview]
Message-ID: <20250622213509.277798-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250622213509.277798-1-richard.henderson@linaro.org>

Do not assume SME implies SVE.  Ensure that the
non-streaming check is present along the SME path,
since it is not implied by sme_*_enabled_check.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-a64.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bb49a2ce90..d7b0c81773 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1387,11 +1387,8 @@ static bool fp_access_check_only(DisasContext *s)
     return true;
 }
 
-static bool fp_access_check(DisasContext *s)
+static bool nonstreaming_check(DisasContext *s)
 {
-    if (!fp_access_check_only(s)) {
-        return false;
-    }
     if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
         gen_exception_insn(s, 0, EXCP_UDEF,
                            syn_smetrap(SME_ET_Streaming, false));
@@ -1400,6 +1397,11 @@ static bool fp_access_check(DisasContext *s)
     return true;
 }
 
+static bool fp_access_check(DisasContext *s)
+{
+    return fp_access_check_only(s) && nonstreaming_check(s);
+}
+
 /*
  * Return <0 for non-supported element sizes, with MO_16 controlled by
  * FEAT_FP16; return 0 for fp disabled; otherwise return >0 for success.
@@ -1450,11 +1452,20 @@ static int fp_access_check_vector_hsd(DisasContext *s, bool is_q, MemOp esz)
  */
 bool sve_access_check(DisasContext *s)
 {
-    if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) {
-        bool ret;
+    bool ret;
 
-        assert(dc_isar_feature(aa64_sme, s));
-        ret = sme_sm_enabled_check(s);
+    switch (dc_isar_feature(aa64_sme, s)) {
+    case true:
+        if (s->pstate_sm) {
+            ret = sme_enabled_check(s);
+        } else if (!dc_isar_feature(aa64_sve, s)) {
+            ret = sme_sm_enabled_check(s);
+        } else {
+            break;
+        }
+        if (ret) {
+            ret = nonstreaming_check(s);
+        }
         s->sve_access_checked = (ret ? 1 : -1);
         return ret;
     }
-- 
2.43.0



  parent reply	other threads:[~2025-06-22 21:36 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-22 21:35 [PATCH v2 0/3] target/arm: SME1/SVE2 fixes Richard Henderson
2025-06-22 21:35 ` [PATCH v2 1/3] target/arm: Fix SME vs AdvSIMD exception priority Richard Henderson
2025-06-24 13:05   ` Peter Maydell
2025-06-22 21:35 ` Richard Henderson [this message]
2025-06-24 13:58   ` [PATCH v2 2/3] target/arm: Fix sve_access_check for SME Peter Maydell
2025-06-24 14:41     ` Richard Henderson
2025-06-22 21:35 ` [PATCH v2 3/3] target/arm: Fix 128-bit element ZIP, UZP, TRN Richard Henderson
2025-06-24 14:59   ` Peter Maydell
2025-06-24 19:04     ` Richard Henderson

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