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From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "pbonzini@redhat.com" <pbonzini@redhat.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	"david@redhat.com" <david@redhat.com>,
	"mst@redhat.com" <mst@redhat.com>,
	"jasowang@redhat.com" <jasowang@redhat.com>,
	"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
	"kevin.tian@intel.com" <kevin.tian@intel.com>,
	"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
	"tjeznach@rivosinc.com" <tjeznach@rivosinc.com>,
	"minwoo.im@samsung.com" <minwoo.im@samsung.com>,
	Ethan MILON <ethan.milon@eviden.com>,
	CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Subject: [PATCH 01/10] pci: Add a memory attribute for pre-translated DMA operations
Date: Sat, 28 Jun 2025 18:03:58 +0000	[thread overview]
Message-ID: <20250628180226.133285-2-clement.mathieu--drif@eviden.com> (raw)
In-Reply-To: <20250628180226.133285-1-clement.mathieu--drif@eviden.com>

The address_type bit will be set to PCI_AT_TRANSLATED by devices that
use cached addresses obtained via ATS.

Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
 include/exec/memattrs.h | 3 +++
 include/hw/pci/pci.h    | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 8db1d30464..52ee955249 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -54,6 +54,9 @@ typedef struct MemTxAttrs {
      */
     unsigned int pid:8;
 
+    /* PCI - IOMMU operations, see PCIAddressType */
+    unsigned int address_type:1;
+
     /*
      * Bus masters which don't specify any attributes will get this
      * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index df3cc7b875..6b7d3ac8a3 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -134,6 +134,15 @@ struct PCIHostDeviceAddress {
     unsigned int function;
 };
 
+/*
+ * Represents the Address Type (AT) field in a PCI request,
+ * see MemTxAttrs.address_type
+ */
+typedef enum PCIAddressType {
+    PCI_AT_UNTRANSLATED = 0, /* Default when no attribute is set */
+    PCI_AT_TRANSLATED = 1,
+} PCIAddressType;
+
 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
                                 uint32_t address, uint32_t data, int len);
 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
-- 
2.49.0


  reply	other threads:[~2025-06-28 18:05 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-28 18:03 [PATCH v5 00/10] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
2025-06-28 18:03 ` CLEMENT MATHIEU--DRIF [this message]
2025-06-28 18:03 ` [PATCH 02/10] memory: Add permissions in IOMMUAccessFlags CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 03/10] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 04/10] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 05/10] intel_iommu: Declare supported PASID size CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 06/10] intel_iommu: Implement vtd_get_iotlb_info from PCIIOMMUOps CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 07/10] intel_iommu: Implement the PCIIOMMUOps callbacks related to invalidations of device-IOTLB CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 08/10] intel_iommu: Return page walk level even when the translation fails CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 09/10] intel_iommu: Set address mask when a translation fails and adjust W permission CLEMENT MATHIEU--DRIF
2025-06-28 18:04 ` [PATCH 10/10] intel_iommu: Add support for ATS CLEMENT MATHIEU--DRIF

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