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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c7fb20esm13701993f8f.36.2025.07.01.07.47.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Jul 2025 07:47:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Julian Armistead , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 66/68] accel/system: Pass old/new interrupt mask to handle_interrupt() handler Date: Tue, 1 Jul 2025 16:40:14 +0200 Message-ID: <20250701144017.43487-67-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250701144017.43487-1-philmd@linaro.org> References: <20250701144017.43487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Update CPUState::interrupt_request once in cpu_interrupt(). Pass the old and new masks along. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops-icount.h | 2 +- accel/tcg/tcg-accel-ops.h | 2 +- include/system/accel-ops.h | 2 +- accel/tcg/tcg-accel-ops-icount.c | 8 +++----- accel/tcg/tcg-accel-ops.c | 4 +--- system/cpus.c | 12 +++++++----- 6 files changed, 14 insertions(+), 16 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-icount.h b/accel/tcg/tcg-accel-ops-icount.h index 5f3ebea50ff..ddd53cc1e4f 100644 --- a/accel/tcg/tcg-accel-ops-icount.h +++ b/accel/tcg/tcg-accel-ops-icount.h @@ -15,6 +15,6 @@ void icount_prepare_for_run(CPUState *cpu); void icount_update_percpu_budget(CPUState *cpu, int cpu_count); void icount_process_data(CPUState *cpu); -void icount_handle_interrupt(CPUState *cpu, int mask); +void icount_handle_interrupt(CPUState *cpu, int old_mask, int new_mask); #endif /* TCG_ACCEL_OPS_ICOUNT_H */ diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index 1263a666774..a95d97fca29 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -17,7 +17,7 @@ void tcg_vcpu_thread_precreate(CPUState *cpu); void tcg_cpu_destroy(CPUState *cpu); int tcg_cpu_exec(CPUState *cpu); -void tcg_handle_interrupt(CPUState *cpu, int mask); +void tcg_handle_interrupt(CPUState *cpu, int old_mask, int new_mask); void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); int tcg_vcpu_init(CPUState *cpu); diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index f98a1c9b662..9d2577fe67f 100644 --- a/include/system/accel-ops.h +++ b/include/system/accel-ops.h @@ -70,7 +70,7 @@ struct AccelOpsClass { void (*synchronize_state)(CPUState *cpu); void (*synchronize_pre_loadvm)(CPUState *cpu); - void (*handle_interrupt)(CPUState *cpu, int mask); + void (*handle_interrupt)(CPUState *cpu, int old_mask, int new_mask); void (*get_vcpu_stats)(CPUState *cpu, GString *buf); diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index ae1297ff7f3..d02b319951c 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -147,14 +147,12 @@ void icount_process_data(CPUState *cpu) replay_mutex_unlock(); } -void icount_handle_interrupt(CPUState *cpu, int mask) +void icount_handle_interrupt(CPUState *cpu, int old_mask, int new_mask) { - int old_mask = cpu->interrupt_request; - - tcg_handle_interrupt(cpu, mask); + tcg_handle_interrupt(cpu, old_mask, new_mask); if (qemu_cpu_is_self(cpu) && !cpu->neg.can_do_io - && (mask & ~old_mask) != 0) { + && (new_mask & ~old_mask) != 0) { cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index c6b5a567f9d..e7716dbc8da 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -109,10 +109,8 @@ static void tcg_cpu_reset_hold(CPUState *cpu) } /* mask must never be zero, except for A20 change call */ -void tcg_handle_interrupt(CPUState *cpu, int mask) +void tcg_handle_interrupt(CPUState *cpu, int old_mask, int new_mask) { - cpu->interrupt_request |= mask; - /* * If called from iothread context, wake the target cpu in * case its halted. diff --git a/system/cpus.c b/system/cpus.c index c2ad640980c..8c2647f5f19 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -246,10 +246,8 @@ int64_t cpus_get_elapsed_ticks(void) return cpu_get_ticks(); } -static void generic_handle_interrupt(CPUState *cpu, int mask) +static void generic_handle_interrupt(CPUState *cpu, int old_mask, int new_mask) { - cpu->interrupt_request |= mask; - if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } @@ -257,12 +255,16 @@ static void generic_handle_interrupt(CPUState *cpu, int mask) void cpu_interrupt(CPUState *cpu, int mask) { + int old_mask = cpu->interrupt_request; + g_assert(bql_locked()); + cpu->interrupt_request |= mask; + if (cpus_accel->handle_interrupt) { - cpus_accel->handle_interrupt(cpu, mask); + cpus_accel->handle_interrupt(cpu, old_mask, cpu->interrupt_request); } else { - generic_handle_interrupt(cpu, mask); + generic_handle_interrupt(cpu, old_mask, cpu->interrupt_request); } } -- 2.49.0