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From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Tan Siewert" <tan@siewert.io>,
	"Jamin Lin" <jamin_lin@aspeedtech.com>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 05/11] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly
Date: Fri,  4 Jul 2025 10:37:17 +0200	[thread overview]
Message-ID: <20250704083723.1410455-6-clg@redhat.com> (raw)
In-Reply-To: <20250704083723.1410455-1-clg@redhat.com>

From: Tan Siewert <tan@siewert.io>

The AST2600 SCU has two protection key registers (0x00 and 0x10) that
both need to be unlocked. (Un-)locking 0x00 modifies both protection key
registers, while modifying 0x10 only modifies itself.

This commit updates the SCU write logic to reject writes unless both
protection key registers are unlocked, matching the behaviour of
real hardware.

Signed-off-by: Tan Siewert <tan@siewert.io>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20250619085329.42125-1-tan@siewert.io
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/misc/aspeed_scu.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 11d073910882..a0ab5eed8f17 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -91,6 +91,7 @@
 #define BMC_DEV_ID           TO_REG(0x1A4)
 
 #define AST2600_PROT_KEY          TO_REG(0x00)
+#define AST2600_PROT_KEY2         TO_REG(0x10)
 #define AST2600_SILICON_REV       TO_REG(0x04)
 #define AST2600_SILICON_REV2      TO_REG(0x14)
 #define AST2600_SYS_RST_CTRL      TO_REG(0x40)
@@ -723,6 +724,8 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
     int reg = TO_REG(offset);
     /* Truncate here so bitwise operations below behave as expected */
     uint32_t data = data64;
+    bool prot_data_state = data == ASPEED_SCU_PROT_KEY;
+    bool unlocked = s->regs[AST2600_PROT_KEY] && s->regs[AST2600_PROT_KEY2];
 
     if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -731,15 +734,24 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
         return;
     }
 
-    if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
+    if ((reg != AST2600_PROT_KEY && reg != AST2600_PROT_KEY2) && !unlocked) {
         qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
+        return;
     }
 
     trace_aspeed_scu_write(offset, size, data);
 
     switch (reg) {
     case AST2600_PROT_KEY:
-        s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
+        /*
+         * Writing a value to SCU000 will modify both protection
+         * registers to each protection register individually.
+         */
+        s->regs[AST2600_PROT_KEY] = prot_data_state;
+        s->regs[AST2600_PROT_KEY2] = prot_data_state;
+        return;
+    case AST2600_PROT_KEY2:
+        s->regs[AST2600_PROT_KEY2] = prot_data_state;
         return;
     case AST2600_HW_STRAP1:
     case AST2600_HW_STRAP2:
-- 
2.50.0



  parent reply	other threads:[~2025-07-04  8:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-04  8:37 [PULL 00/11] aspeed queue Cédric Le Goater
2025-07-04  8:37 ` [PULL 01/11] hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700 Cédric Le Goater
2025-07-04  8:37 ` [PULL 02/11] hw/misc/aspeed_scu: Support the Frequency Counter Control register " Cédric Le Goater
2025-07-04  8:37 ` [PULL 03/11] hw/arm/aspeed: bletchley: update hw strap values Cédric Le Goater
2025-07-04  8:37 ` [PULL 04/11] hw/arm/aspeed: add Catalina machine type Cédric Le Goater
2025-07-04  8:37 ` Cédric Le Goater [this message]
2025-07-04  8:37 ` [PULL 06/11] tests/qtest: Add test for ASPEED SCU Cédric Le Goater
2025-07-04  8:37 ` [PULL 07/11] aspeed: Deprecate the ast2700a0-evb machine Cédric Le Goater
2025-07-04  8:37 ` [PULL 08/11] hw/arm/aspeed: Add second SPI chip to Aspeed model Cédric Le Goater
2025-07-04  8:37 ` [PULL 09/11] docs: add support for gb200-bmc Cédric Le Goater
2025-07-11 12:01   ` Peter Maydell
2025-07-15  6:13     ` Cédric Le Goater
2025-07-15  8:49       ` Peter Maydell
2025-07-04  8:37 ` [PULL 10/11] hw/arm/aspeed: Add GB200 BMC target Cédric Le Goater
2025-07-04  8:37 ` [PULL 11/11] tests/functional: Add gb200 tests Cédric Le Goater
2025-07-04 17:49 ` [PULL 00/11] aspeed queue Stefan Hajnoczi

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