From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 16/20] target/arm: Introduce get_phys_addr_for_at
Date: Mon, 7 Jul 2025 14:21:07 -0600 [thread overview]
Message-ID: <20250707202111.293787-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250707202111.293787-1-richard.henderson@linaro.org>
Rename get_phys_addr_with_space_nogpc for its only
caller, do_ats_write. Drop the MemOp memop argument
as it doesn't make sense in the new context.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 17 +++++++----------
target/arm/ptw.c | 17 ++++++++++-------
target/arm/tcg/cpregs-at.c | 9 ++-------
3 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0844048ee8..6aea942d06 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1584,25 +1584,22 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
__attribute__((nonnull));
/**
- * get_phys_addr_with_space_nogpc: get the physical address for a virtual
- * address
+ * get_phys_addr_for_at:
* @env: CPUARMState
* @address: virtual address to get physical address for
* @access_perm: PAGE_{READ,WRITE,EXEC}, or 0
- * @memop: memory operation feeding this access, or 0 for none
* @mmu_idx: MMU index indicating required translation regime
* @space: security space for the access
* @result: set on translation success.
* @fi: set to fault info if the translation fails
*
- * Similar to get_phys_addr, but use the given security space and don't perform
- * a Granule Protection Check on the resulting address.
+ * Similar to get_phys_addr, but for use by AccessType_AT, i.e.
+ * system instructions for address translation.
*/
-bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address,
- unsigned access_perm, MemOp memop,
- ARMMMUIdx mmu_idx, ARMSecuritySpace space,
- GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+bool get_phys_addr_for_at(CPUARMState *env, vaddr address,
+ unsigned access_perm, ARMMMUIdx mmu_idx,
+ ARMSecuritySpace space, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
__attribute__((nonnull));
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index c1fe53965c..19a53ec707 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3538,18 +3538,21 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw,
return false;
}
-bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address,
- unsigned access_perm, MemOp memop,
- ARMMMUIdx mmu_idx, ARMSecuritySpace space,
- GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+bool get_phys_addr_for_at(CPUARMState *env, vaddr address,
+ unsigned access_perm, ARMMMUIdx mmu_idx,
+ ARMSecuritySpace space, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
{
S1Translate ptw = {
.in_mmu_idx = mmu_idx,
.in_space = space,
};
- return get_phys_addr_nogpc(env, &ptw, address, access_perm,
- memop, result, fi);
+ /*
+ * I_MXTJT: Granule protection checks are not performed on the final
+ * address of a successful translation. This is a translation not a
+ * memory reference, so "memop = none = 0".
+ */
+ return get_phys_addr_nogpc(env, &ptw, address, access_perm, 0, result, fi);
}
static ARMSecuritySpace
diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c
index c34fc6ec6f..e79866e651 100644
--- a/target/arm/tcg/cpregs-at.c
+++ b/target/arm/tcg/cpregs-at.c
@@ -33,13 +33,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
ARMMMUFaultInfo fi = {};
GetPhysAddrResult res = {};
- /*
- * I_MXTJT: Granule protection checks are not performed on the final
- * address of a successful translation. This is a translation not a
- * memory reference, so "memop = none = 0".
- */
- ret = get_phys_addr_with_space_nogpc(env, value, 1 << access_type, 0,
- mmu_idx, ss, &res, &fi);
+ ret = get_phys_addr_for_at(env, value, 1 << access_type,
+ mmu_idx, ss, &res, &fi);
/*
* ATS operations only do S1 or S1+S2 translations, so we never
--
2.43.0
next prev parent reply other threads:[~2025-07-07 21:04 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-07 20:20 [PATCH 00/20] target/arm: Implement FEAT_ATS1A Richard Henderson
2025-07-07 20:20 ` [PATCH 01/20] target/arm: Convert get_phys_addr_v5 to access_perm Richard Henderson
2025-07-07 20:20 ` [PATCH 02/20] target/arm: Convert get_phys_addr_v6 " Richard Henderson
2025-07-07 20:20 ` [PATCH 03/20] target/arm: Convert get_phys_addr_lpae " Richard Henderson
2025-07-10 11:59 ` Peter Maydell
2025-07-10 15:06 ` Richard Henderson
2025-07-07 20:20 ` [PATCH 04/20] target/arm: Convert get_phys_addr_pmsav5 " Richard Henderson
2025-07-07 20:20 ` [PATCH 05/20] target/arm: Convert get_phys_addr_pmsav7 " Richard Henderson
2025-07-07 20:20 ` [PATCH 06/20] target/arm: Convert pmsav8_mpu_lookup " Richard Henderson
2025-07-07 20:20 ` [PATCH 07/20] target/arm: Convert v8m_is_sau_exempt " Richard Henderson
2025-07-10 12:01 ` Peter Maydell
2025-07-10 16:19 ` Richard Henderson
2025-07-07 20:20 ` [PATCH 08/20] target/arm: Convert v8m_security_lookup " Richard Henderson
2025-07-07 20:21 ` [PATCH 09/20] target/arm: Convert get_phys_addr_pmsav8 " Richard Henderson
2025-07-07 20:21 ` [PATCH 10/20] target/arm: Convert get_phys_addr_disabled " Richard Henderson
2025-07-07 20:21 ` [PATCH 11/20] target/arm: Convert get_phys_addr_nogpc " Richard Henderson
2025-07-07 20:21 ` [PATCH 12/20] target/arm: Convert get_phys_addr_gpc " Richard Henderson
2025-07-07 20:21 ` [PATCH 13/20] target/arm: Convert get_phys_addr_with_space_nogpc " Richard Henderson
2025-07-07 20:21 ` [PATCH 14/20] target/arm: Convert get_phys_addr " Richard Henderson
2025-07-07 20:21 ` [PATCH 15/20] target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug Richard Henderson
2025-07-07 20:21 ` Richard Henderson [this message]
2025-07-07 20:21 ` [PATCH 17/20] target/arm: Skip AF and DB updates for AccessType_AT Richard Henderson
2025-07-07 20:21 ` [PATCH 18/20] target/arm: Convert do_ats_write to access_perm Richard Henderson
2025-07-07 20:21 ` [PATCH 19/20] target/arm: Fill in HFGITR_EL2 bits for Arm v9.5 Richard Henderson
2025-07-07 20:21 ` [PATCH 20/20] target/arm: Implement FEAT_ATS1A Richard Henderson
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