From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC7D4C8303C for ; Tue, 8 Jul 2025 21:26:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFH-0002W9-Le; Tue, 08 Jul 2025 16:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrh-00007s-Bl for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:36 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrb-0008BN-UV for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002424; x=1783538424; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YN0+Qrax2R2/lK61bIWyywAa1Rg9ofrCC/jNHMSnzkg=; b=Ld9EhXVjiUwOk9OX0/ZOf5hcUTOKWBxbliTUG3PaAz2e4ipMIgrg0Z6j C7f4JsD6ZhWJbUS4gpdEcIBUyueA3EmHQXwJ0OYZiHtJCfg2yXNqaS+aq 4R25uklmvp0ISO6YbgPLNttpVciuqv8u2aY6SZ+Hhz+leV33w63mMjWy4 qwDbftn2ikj1Mu84ZCwEnf2q2A62HEuftwYqQMbvpCLLvjUOdfzYtJGul KjUg9/IuTrbV0GnJT6UC88twqC4Nnl7JesN09s+AxoM8g6eS7B6Yvh6Wy Xjj394Fc0k/G/tQCvkOsHntitNohPWrTq1AA++L45AFld5lOnY3mRDiHL A==; X-CSE-ConnectionGUID: xxniA8btTiuthwLjHyrYEQ== X-CSE-MsgGUID: N7gOda2vTBmflCT5th6xdw== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974005" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974005" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:51 -0700 X-CSE-ConnectionGUID: hK44WR2KTFGJU6LuIKQCsw== X-CSE-MsgGUID: WArYOA3xQPuYb+sLVJpQjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647964" Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:46 -0700 From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 09/20] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Date: Tue, 8 Jul 2025 07:05:50 -0400 Message-ID: <20250708110601.633308-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PCI device supports two request types, Requests-without-PASID and Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's pasid to index pasid table. So we need to translate between PCI's pasid and IOMMU's pasid specially for Requests-without-PASID, e.g., PCI_NO_PASID(-1) <-> rid_pasid. For Requests-with-PASID, PCI's pasid and IOMMU's pasid are same value. vtd_as_from_iommu_pasid_locked() translates from BDF+iommu_pasid to vtd_as which contains PCI's pasid vtd_as->pasid. vtd_as_to_iommu_pasid_locked() translates from BDF+vtd_as->pasid to iommu_pasid. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 15f4393d6f..38e7f7b7be 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1602,6 +1602,64 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, return 0; } +static int vtd_as_to_iommu_pasid_locked(VTDAddressSpace *vtd_as, + uint32_t *pasid) +{ + VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry; + IntelIOMMUState *s = vtd_as->iommu_state; + uint8_t bus_num = pci_bus_num(vtd_as->bus); + uint8_t devfn = vtd_as->devfn; + VTDContextEntry ce; + int ret; + + if (cc_entry->context_cache_gen == s->context_cache_gen) { + ce = cc_entry->context_entry; + } else { + ret = vtd_dev_to_context_entry(s, bus_num, devfn, &ce); + if (ret) { + return ret; + } + } + + /* Translate to iommu pasid if PCI_NO_PASID */ + if (vtd_as->pasid == PCI_NO_PASID) { + *pasid = VTD_CE_GET_RID2PASID(&ce); + } else { + *pasid = vtd_as->pasid; + } + + return 0; +} + +static gboolean vtd_find_as_by_sid_and_iommu_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDAddressSpace *vtd_as = (VTDAddressSpace *)value; + struct vtd_as_raw_key *target = (struct vtd_as_raw_key *)user_data; + uint16_t sid = PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn); + uint32_t pasid; + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return false; + } + + return (pasid == target->pasid) && (sid == target->sid); +} + +/* Translate iommu pasid to vtd_as */ +static inline +VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, uint32_t pasid) +{ + struct vtd_as_raw_key key = { + .sid = sid, + .pasid = pasid + }; + + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_iommu_pasid, &key); +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { -- 2.47.1