From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19F4FC8303C for ; Tue, 8 Jul 2025 21:22:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFE-0002D3-5T; Tue, 08 Jul 2025 16:48:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrb-0008SS-Az for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:24 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrQ-0008BN-BI for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002413; x=1783538413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JvvhniYOGljHl/kopdCojhByjmKO1fjRQmn9E59WiUY=; b=gZnIDcaYJg9GtvOUSsrIfmNzkLQ1hzkxdYMxoLXwUszyuonRWJHzjhM8 0usHviO4mIY3VUHGhTmN3mm7p322Qa4jLEWLGTQ2ztdxx+sx6kCrS/69h 6V9fWhiz7aUqYRH7BHQjwh6sTARegwQjHNA74d8k+o3RDVMW3lBWpymXi 2lptFxlFqyYbgxcw0OGqo668As5RU4r4eDdoxDFpn2kqS3vK9Uw/FxfBG VgBrpURJkIBVjPyes0blKcoR+f3oVesN3CLh9Rjvn41E5JFNNrvh/r04S PRVUMt+/kLkwKmrNxob9UEwsaRj3/cfh4sOJI6L+AG6siyCJp7Q+mnhhU g==; X-CSE-ConnectionGUID: EY0Sa3PwRHOpfgOt6JVfKA== X-CSE-MsgGUID: JdjI7dE/Tpi/AnD5dM/uoQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973960" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973960" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:37 -0700 X-CSE-ConnectionGUID: egwCBXf5QbOpKzbG/n3EaQ== X-CSE-MsgGUID: cOZ9T2MbRcap460ODKMmBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647949" Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:33 -0700 From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 06/20] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Date: Tue, 8 Jul 2025 07:05:47 -0400 Message-ID: <20250708110601.633308-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 15 +++++++++++++-- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 702973da5c..e90fd2f28f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gconstpointer v2) static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod = v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4360,6 +4363,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s = opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key = { .bus = bus, .devfn = devfn, @@ -4376,7 +4380,14 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, return false; } + vtd_hiod = g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus = bus; + vtd_hiod->devfn = (uint8_t)devfn; + vtd_hiod->iommu_state = s; + vtd_hiod->hiod = hiod; + if (!vtd_check_hiod(s, hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } @@ -4386,7 +4397,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, new_key->devfn = devfn; object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); vtd_iommu_unlock(s); diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..7aba259ef8 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" /* * Intel IOMMU register specification @@ -607,4 +608,10 @@ typedef struct VTDRootEntry VTDRootEntry; /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..50f9b27a45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -295,7 +295,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ -- 2.47.1