* [PATCH v2 1/9] i386/cpu: Introduce cache model for SierraForest
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
@ 2025-07-11 10:45 ` Zhao Liu
2025-07-11 10:45 ` [PATCH v2 2/9] i386/cpu: Introduce cache model for GraniteRapids Zhao Liu
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:45 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi, Tao Su
Add the cache model to SierraForest (v3) to better emulate its
environment.
The cache model is based on SierraForest-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x80 (128)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 128
(size synth) = 65536 (64 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x7 (7)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x1000 (4096)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 4096
(size synth) = 4194304 (4 MB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1ff (511)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0xc (12)
number of sets = 0x24000 (147456)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = true
number of sets (s) = 147456
(size synth) = 113246208 (108 MB)
--- cache 4 ---
cache type = no more caches (0)
Suggested-by: Tejus GK <tejus.gk@nutanix.com>
Suggested-by: Jason Zeng <jason.zeng@intel.com>
Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f88fe0c8697..a97ee3c2af43 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2878,6 +2878,97 @@ static const CPUCaches epyc_turin_cache_info = {
.no_invd_sharing = true,
.complex_indexing = false,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
+ }
+};
+
+static const CPUCaches xeon_srf_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x0.EAX */
+ .type = DATA_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x0.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x0.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x0.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 32 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x1.EAX */
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x1.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x1.ECX */
+ .sets = 128,
+
+ /* CPUID 0x4.0x1.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 64 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x2.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .self_init = true,
+
+ /* CPUID 0x4.0x2.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x2.ECX */
+ .sets = 4096,
+
+ /* CPUID 0x4.0x2.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 4 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_MODULE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x3.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .self_init = true,
+
+ /* CPUID 0x4.0x3.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 12,
+
+ /* CPUID 0x4.0x3.ECX */
+ .sets = 147456,
+
+ /* CPUID 0x4.0x3.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = true,
+
+ .size = 108 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
},
};
@@ -5003,6 +5094,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .note = "with srf-sp cache model",
+ .cache_info = &xeon_srf_cache_info,
+ },
{ /* end of list */ },
},
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 2/9] i386/cpu: Introduce cache model for GraniteRapids
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
2025-07-11 10:45 ` [PATCH v2 1/9] i386/cpu: Introduce cache model for SierraForest Zhao Liu
@ 2025-07-11 10:45 ` Zhao Liu
2025-07-11 10:45 ` [PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids Zhao Liu
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:45 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi, Tao Su
Add the cache model to GraniteRapids (v3) to better emulate its
environment.
The cache model is based on GraniteRapids-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0xc (12)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 49152 (48 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 65536 (64 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x800 (2048)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 2048
(size synth) = 2097152 (2 MB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0xff (255)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x48000 (294912)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = true
number of sets (s) = 294912
(size synth) = 301989888 (288 MB)
--- cache 4 ---
cache type = no more caches (0)
Suggested-by: Tejus GK <tejus.gk@nutanix.com>
Suggested-by: Jason Zeng <jason.zeng@intel.com>
Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a97ee3c2af43..4ce063fb6492 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2881,6 +2881,97 @@ static const CPUCaches epyc_turin_cache_info = {
}
};
+static const CPUCaches xeon_gnr_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x0.EAX */
+ .type = DATA_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x0.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 12,
+
+ /* CPUID 0x4.0x0.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x0.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 48 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x1.EAX */
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x1.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x1.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x1.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 64 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x2.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .self_init = true,
+
+ /* CPUID 0x4.0x2.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x2.ECX */
+ .sets = 2048,
+
+ /* CPUID 0x4.0x2.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 2 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x3.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .self_init = true,
+
+ /* CPUID 0x4.0x3.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x3.ECX */
+ .sets = 294912,
+
+ /* CPUID 0x4.0x3.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = true,
+
+ .size = 288 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
+ },
+};
+
static const CPUCaches xeon_srf_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
/* CPUID 0x4.0x0.EAX */
@@ -4949,6 +5040,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .note = "with gnr-sp cache model",
+ .cache_info = &xeon_gnr_cache_info,
+ },
{ /* end of list */ },
},
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
2025-07-11 10:45 ` [PATCH v2 1/9] i386/cpu: Introduce cache model for SierraForest Zhao Liu
2025-07-11 10:45 ` [PATCH v2 2/9] i386/cpu: Introduce cache model for GraniteRapids Zhao Liu
@ 2025-07-11 10:45 ` Zhao Liu
2025-07-11 10:45 ` [PATCH v2 4/9] i386/cpu: Introduce cache model for YongFeng Zhao Liu
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:45 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi, Tao Su
Add the cache model to SapphireRapids (v4) to better emulate its
environment.
The cache model is based on SapphireRapids-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0xc (12)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 49152 (48 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x800 (2048)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 2048
(size synth) = 2097152 (2 MB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x7f (127)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0xf (15)
number of sets = 0x10000 (65536)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = true
number of sets (s) = 65536
(size synth) = 62914560 (60 MB)
--- cache 4 ---
cache type = no more caches (0)
Suggested-by: Tejus GK <tejus.gk@nutanix.com>
Suggested-by: Jason Zeng <jason.zeng@intel.com>
Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4ce063fb6492..e9f3434b096c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2881,6 +2881,97 @@ static const CPUCaches epyc_turin_cache_info = {
}
};
+static const CPUCaches xeon_spr_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x0.EAX */
+ .type = DATA_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x0.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 12,
+
+ /* CPUID 0x4.0x0.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x0.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 48 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x1.EAX */
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x1.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x1.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x1.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 32 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x2.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .self_init = true,
+
+ /* CPUID 0x4.0x2.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x2.ECX */
+ .sets = 2048,
+
+ /* CPUID 0x4.0x2.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 2 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x3.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .self_init = true,
+
+ /* CPUID 0x4.0x3.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 15,
+
+ /* CPUID 0x4.0x3.ECX */
+ .sets = 65536,
+
+ /* CPUID 0x4.0x3.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = true,
+
+ .size = 60 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
+ },
+};
+
static const CPUCaches xeon_gnr_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
/* CPUID 0x4.0x0.EAX */
@@ -4887,6 +4978,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 4,
+ .note = "with spr-sp cache model",
+ .cache_info = &xeon_spr_cache_info,
+ },
{ /* end of list */ }
}
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 4/9] i386/cpu: Introduce cache model for YongFeng
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (2 preceding siblings ...)
2025-07-11 10:45 ` [PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids Zhao Liu
@ 2025-07-11 10:45 ` Zhao Liu
2025-07-11 10:45 ` [PATCH v2 5/9] i386/cpu: Add a "x-force-cpuid-0x1f" property Zhao Liu
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:45 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu
From: Ewan Hai <ewanhai-oc@zhaoxin.com>
Add the cache model to YongFeng (v3) to better emulate its
environment.
Note, although YongFeng v2 was added after v10.0, it was also back
ported to v10.0.2. Therefore, the new version (v3) is needed to avoid
conflict.
The cache model is as follows:
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x0 (0)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x0 (0)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 65536 (64 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x0 (0)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x0 (0)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x2000 (8192)
WBINVD/INVD acts on lower caches = true
inclusive to lower caches = true
complex cache indexing = false
number of sets (s) = 8192
(size synth) = 8388608 (8 MB)
--- cache 4 ---
cache type = no more caches (0)
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes Since v1:
* Polish the note.
Changes on the original codes:
* Rearrange cache model fields to make them easier to check.
* And add explanation of why v3 is needed.
* Drop lines_per_tag field for L2 & L3.
---
target/i386/cpu.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e9f3434b096c..5676e5526f40 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3154,6 +3154,105 @@ static const CPUCaches xeon_srf_cache_info = {
},
};
+static const CPUCaches yongfeng_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x0.EAX */
+ .type = DATA_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x0.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x0.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x0.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ /* CPUID 0x80000005.ECX */
+ .lines_per_tag = 1,
+ .size = 32 * KiB,
+
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x1.EAX */
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x1.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x1.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x1.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ /* CPUID 0x80000005.EDX */
+ .lines_per_tag = 1,
+ .size = 64 * KiB,
+
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x2.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .self_init = true,
+
+ /* CPUID 0x4.0x2.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x2.ECX */
+ .sets = 512,
+
+ /* CPUID 0x4.0x2.EDX */
+ .no_invd_sharing = false,
+ .inclusive = true,
+ .complex_indexing = false,
+
+ /* CPUID 0x80000006.ECX */
+ .size = 256 * KiB,
+
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x3.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .self_init = true,
+
+ /* CPUID 0x4.0x3.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x3.ECX */
+ .sets = 8192,
+
+ /* CPUID 0x4.0x3.EDX */
+ .no_invd_sharing = true,
+ .inclusive = true,
+ .complex_indexing = false,
+
+ .size = 8 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
+ },
+};
+
/* The following VMX features are not supported by KVM and are left out in the
* CPU definitions:
*
@@ -6433,6 +6532,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .note = "with the cache model",
+ .cache_info = &yongfeng_cache_info,
+ },
{ /* end of list */ }
}
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 5/9] i386/cpu: Add a "x-force-cpuid-0x1f" property
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (3 preceding siblings ...)
2025-07-11 10:45 ` [PATCH v2 4/9] i386/cpu: Introduce cache model for YongFeng Zhao Liu
@ 2025-07-11 10:45 ` Zhao Liu
2025-07-11 10:46 ` [PATCH v2 6/9] i386/cpu: Enable 0x1f leaf for SierraForest by default Zhao Liu
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:45 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi
From: Manish Mishra <manish.mishra@nutanix.com>
Add a "x-force-cpuid-0x1f" property so that CPU models can enable it and
have 0x1f CPUID leaf natually as the Host CPU.
The advantage is that when the CPU model's cache model is already
consistent with the Host CPU, for example, SRF defaults to l2 per
module & l3 per package, 0x1f can better help users identify the
topology in the VM.
Adding 0x1f for specific CPU models should not cause any trouble in
principle. This property is only enabled for CPU models that already
have 0x1f leaf on the Host, so software that originally runs normally on
the Host won't encounter issues in the Guest with corresponding CPU
model. Conversely, some software that relies on checking 0x1f might
have problems in the Guest due to the lack of 0x1f [*]. In
summary, adding 0x1f is also intended to further emulate the Host CPU
environment.
[*]: https://lore.kernel.org/qemu-devel/PH0PR02MB738410511BF51B12DB09BE6CF6AC2@PH0PR02MB7384.namprd02.prod.outlook.com/
Signed-off-by: Manish Mishra <manish.mishra@nutanix.com>
Co-authored-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
[Integrated and rebased 2 previous patches (ordered by post time)]
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Note:
This patch integrates the idea from 2 previous posted patches (ordered
by post time)[1] [2], following the s-o-b policy of "Re-starting
abandoned work" in docs/devel/code-provenance.rst.
[1]: From Manish: https://lore.kernel.org/qemu-devel/20240722101859.47408-1-manish.mishra@nutanix.com/
[2]: From Xiaoyao: https://lore.kernel.org/qemu-devel/20240813033145.279307-1-xiaoyao.li@intel.com/
---
Changes since RFC:
* Rebase and rename the property as "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5676e5526f40..d27eeb1cb718 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9940,6 +9940,7 @@ static const Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true),
+ DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false),
};
#ifndef CONFIG_USER_ONLY
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 6/9] i386/cpu: Enable 0x1f leaf for SierraForest by default
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (4 preceding siblings ...)
2025-07-11 10:45 ` [PATCH v2 5/9] i386/cpu: Add a "x-force-cpuid-0x1f" property Zhao Liu
@ 2025-07-11 10:46 ` Zhao Liu
2025-07-11 10:46 ` [PATCH v2 7/9] i386/cpu: Enable 0x1f leaf for GraniteRapids " Zhao Liu
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:46 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi
Host SierraForest CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d27eeb1cb718..2f19726a9397 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5387,8 +5387,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- .note = "with srf-sp cache model",
+ .note = "with srf-sp cache model and 0x1f leaf",
.cache_info = &xeon_srf_cache_info,
+ .props = (PropValue[]) {
+ { "x-force-cpuid-0x1f", "on" },
+ }
},
{ /* end of list */ },
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 7/9] i386/cpu: Enable 0x1f leaf for GraniteRapids by default
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (5 preceding siblings ...)
2025-07-11 10:46 ` [PATCH v2 6/9] i386/cpu: Enable 0x1f leaf for SierraForest by default Zhao Liu
@ 2025-07-11 10:46 ` Zhao Liu
2025-07-11 10:46 ` [PATCH v2 8/9] i386/cpu: Enable 0x1f leaf for SapphireRapids " Zhao Liu
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:46 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi
Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2f19726a9397..02198872ede7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5237,8 +5237,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- .note = "with gnr-sp cache model",
+ .note = "with gnr-sp cache model and 0x1f leaf",
.cache_info = &xeon_gnr_cache_info,
+ .props = (PropValue[]) {
+ { "x-force-cpuid-0x1f", "on" },
+ }
},
{ /* end of list */ },
},
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 8/9] i386/cpu: Enable 0x1f leaf for SapphireRapids by default
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (6 preceding siblings ...)
2025-07-11 10:46 ` [PATCH v2 7/9] i386/cpu: Enable 0x1f leaf for GraniteRapids " Zhao Liu
@ 2025-07-11 10:46 ` Zhao Liu
2025-07-11 10:46 ` [PATCH v2 9/9] i386/cpu: Enable 0x1f leaf for YongFeng " Zhao Liu
2025-07-11 16:51 ` [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Paolo Bonzini
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:46 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu, Dapeng Mi
Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 02198872ede7..44394fa72248 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5079,8 +5079,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- .note = "with spr-sp cache model",
+ .note = "with spr-sp cache model and 0x1f leaf",
.cache_info = &xeon_spr_cache_info,
+ .props = (PropValue[]) {
+ { "x-force-cpuid-0x1f", "on" },
+ }
},
{ /* end of list */ }
}
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 9/9] i386/cpu: Enable 0x1f leaf for YongFeng by default
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (7 preceding siblings ...)
2025-07-11 10:46 ` [PATCH v2 8/9] i386/cpu: Enable 0x1f leaf for SapphireRapids " Zhao Liu
@ 2025-07-11 10:46 ` Zhao Liu
2025-07-11 16:51 ` [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Paolo Bonzini
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-07-11 10:46 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost
Cc: Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel, Zhao Liu
Host YongFeng CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes Since v1:
* New patch suggested by Ewan.
---
target/i386/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 44394fa72248..8d67cadec2f2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6543,8 +6543,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- .note = "with the cache model",
+ .note = "with the cache model and 0x1f leaf",
.cache_info = &yongfeng_cache_info,
+ .props = (PropValue[]) {
+ { "x-force-cpuid-0x1f", "on" },
+ }
},
{ /* end of list */ }
}
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement
2025-07-11 10:45 [PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement Zhao Liu
` (8 preceding siblings ...)
2025-07-11 10:46 ` [PATCH v2 9/9] i386/cpu: Enable 0x1f leaf for YongFeng " Zhao Liu
@ 2025-07-11 16:51 ` Paolo Bonzini
9 siblings, 0 replies; 11+ messages in thread
From: Paolo Bonzini @ 2025-07-11 16:51 UTC (permalink / raw)
To: Zhao Liu
Cc: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Ewan Hai, Jason Zeng, Xiaoyao Li, Tao Su, Yi Lai, Dapeng Mi,
Tejus GK, Manish Mishra, qemu-devel
Queued, thanks.
Paolo
^ permalink raw reply [flat|nested] 11+ messages in thread