* [PATCH v7 01/36] hw/i386/acpi-build: Make aml_pci_device_dsm() static
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 02/36] hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp Eric Auger
` (35 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
No need to export aml_pci_device_dsm() as it is only used
in hw/i386/acpi-build.c.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
include/hw/acpi/pci.h | 1 -
hw/i386/acpi-build.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h
index 6359d574fd..ab0187a894 100644
--- a/include/hw/acpi/pci.h
+++ b/include/hw/acpi/pci.h
@@ -36,7 +36,6 @@ typedef struct AcpiMcfgInfo {
void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info,
const char *oem_id, const char *oem_table_id);
-Aml *aml_pci_device_dsm(void);
void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus);
void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 61851cc840..f59026524f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -338,7 +338,7 @@ build_facs(GArray *table_data)
g_array_append_vals(table_data, reserved, 40); /* Reserved */
}
-Aml *aml_pci_device_dsm(void)
+static Aml *aml_pci_device_dsm(void)
{
Aml *method;
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 02/36] hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
2025-07-14 8:04 ` [PATCH v7 01/36] hw/i386/acpi-build: Make aml_pci_device_dsm() static Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 03/36] hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to acpi_dsdt_add_pci_osc Eric Auger
` (34 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
We plan to reuse build_x86_acpi_pci_hotplug() implementation
for ARM so let's move the code to generic pcihp.
Associated static aml_pci_pdsm() helper is also moved along.
build_x86_acpi_pci_hotplug is renamed into build_acpi_pci_hotplug().
No code change intended.
Also fix the reference to acpi_pci_hotplug.rst documentation
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v1 -> v2:
- s/spec/specs in reference to rst (Gustavo)
- fixed double space in commit msg (Gustavo)
rfc -> v1:
- make build_append_pci_dsm_func0_common non static and move it to
pcihp
---
hw/i386/acpi-build.h | 4 -
include/hw/acpi/pcihp.h | 7 ++
hw/acpi/pcihp.c | 174 ++++++++++++++++++++++++++++++++++++++-
hw/i386/acpi-build.c | 176 +---------------------------------------
4 files changed, 182 insertions(+), 179 deletions(-)
diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
index 275ec058a1..8ba3c33e48 100644
--- a/hw/i386/acpi-build.h
+++ b/hw/i386/acpi-build.h
@@ -5,10 +5,6 @@
extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
-/* PCI Hot-plug registers' base. See docs/specs/acpi_pci_hotplug.rst */
-#define ACPI_PCIHP_SEJ_BASE 0x8
-#define ACPI_PCIHP_BNMR_BASE 0x10
-
void acpi_setup(void);
Object *acpi_get_i386_pci_host(void);
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index cdc0cb8e43..971451e8ea 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -33,6 +33,10 @@
#define ACPI_PCIHP_IO_BASE_PROP "acpi-pcihp-io-base"
#define ACPI_PCIHP_IO_LEN_PROP "acpi-pcihp-io-len"
+/* PCI Hot-plug registers bases. See docs/specs/acpi_pci_hotplug.rst */
+#define ACPI_PCIHP_SEJ_BASE 0x8
+#define ACPI_PCIHP_BNMR_BASE 0x10
+
typedef struct AcpiPciHpPciStatus {
uint32_t up;
uint32_t down;
@@ -69,6 +73,9 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,
AcpiPciHpState *s, DeviceState *dev,
Error **errp);
+void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr);
+void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar);
+
/* Called on reset */
void acpi_pcihp_reset(AcpiPciHpState *s);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 497281ae20..cbe7e01385 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -26,7 +26,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/pcihp.h"
-
+#include "hw/acpi/aml-build.h"
#include "hw/pci-host/i440fx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
@@ -513,6 +513,178 @@ void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
OBJ_PROP_FLAG_READ);
}
+void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
+{
+ Aml *UUID, *ifctx1;
+ uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
+
+ aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6. _DSM Definitions for PCI
+ */
+ UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
+ ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
+ {
+ /* call is for unsupported UUID, bail out */
+ aml_append(ifctx1, aml_return(retvar));
+ }
+ aml_append(ctx, ifctx1);
+
+ ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
+ {
+ /* call is for unsupported REV, bail out */
+ aml_append(ifctx1, aml_return(retvar));
+ }
+ aml_append(ctx, ifctx1);
+}
+
+static Aml *aml_pci_pdsm(void)
+{
+ Aml *method, *ifctx, *ifctx1;
+ Aml *ret = aml_local(0);
+ Aml *caps = aml_local(1);
+ Aml *acpi_index = aml_local(2);
+ Aml *zero = aml_int(0);
+ Aml *one = aml_int(1);
+ Aml *not_supp = aml_int(0xFFFFFFFF);
+ Aml *func = aml_arg(2);
+ Aml *params = aml_arg(4);
+ Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
+ Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
+
+ method = aml_method("PDSM", 5, AML_SERIALIZED);
+
+ /* get supported functions */
+ ifctx = aml_if(aml_equal(func, zero));
+ {
+ build_append_pci_dsm_func0_common(ifctx, ret);
+
+ aml_append(ifctx, aml_store(zero, caps));
+ aml_append(ifctx,
+ aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
+ /*
+ * advertise function 7 if device has acpi-index
+ * acpi_index values:
+ * 0: not present (default value)
+ * FFFFFFFF: not supported (old QEMU without PIDX reg)
+ * other: device's acpi-index
+ */
+ ifctx1 = aml_if(aml_lnot(
+ aml_or(aml_equal(acpi_index, zero),
+ aml_equal(acpi_index, not_supp), NULL)
+ ));
+ {
+ /* have supported functions */
+ aml_append(ifctx1, aml_or(caps, one, caps));
+ /* support for function 7 */
+ aml_append(ifctx1,
+ aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
+ }
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
+ aml_append(ifctx, aml_return(ret));
+ }
+ aml_append(method, ifctx);
+
+ /* handle specific functions requests */
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
+ * Operating Systems
+ */
+ ifctx = aml_if(aml_equal(func, aml_int(7)));
+ {
+ Aml *pkg = aml_package(2);
+
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
+ aml_append(ifctx, aml_store(pkg, ret));
+ /*
+ * Windows calls func=7 without checking if it's available,
+ * as workaround Microsoft has suggested to return invalid for func7
+ * Package, so return 2 elements package but only initialize elements
+ * when acpi_index is supported and leave them uninitialized, which
+ * leads elements to being Uninitialized ObjectType and should trip
+ * Windows into discarding result as an unexpected and prevent setting
+ * bogus 'PCI Label' on the device.
+ */
+ ifctx1 = aml_if(aml_lnot(aml_lor(
+ aml_equal(acpi_index, zero), aml_equal(acpi_index, not_supp)
+ )));
+ {
+ aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
+ /*
+ * optional, if not impl. should return null string
+ */
+ aml_append(ifctx1, aml_store(aml_string("%s", ""),
+ aml_index(ret, one)));
+ }
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_return(ret));
+ }
+
+ aml_append(method, ifctx);
+ return method;
+}
+
+void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
+{
+ Aml *scope;
+ Aml *field;
+ Aml *method;
+
+ scope = aml_scope("_SB.PCI0");
+
+ aml_append(scope,
+ aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
+ field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("PCIU", 32));
+ aml_append(field, aml_named_field("PCID", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("SEJ", AML_SYSTEM_IO,
+ aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
+ field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("B0EJ", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("BNMR", AML_SYSTEM_IO,
+ aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
+ field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("BNUM", 32));
+ aml_append(field, aml_named_field("PIDX", 32));
+ aml_append(scope, field);
+
+ aml_append(scope, aml_mutex("BLCK", 0));
+
+ method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
+ aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
+ aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+ aml_append(method,
+ aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
+ aml_append(method, aml_release(aml_name("BLCK")));
+ aml_append(method, aml_return(aml_int(0)));
+ aml_append(scope, method);
+
+ method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
+ aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
+ aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+ aml_append(method,
+ aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
+ aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
+ aml_append(method, aml_release(aml_name("BLCK")));
+ aml_append(method, aml_return(aml_local(0)));
+ aml_append(scope, method);
+
+ aml_append(scope, aml_pci_pdsm());
+
+ aml_append(table, scope);
+}
+
const VMStateDescription vmstate_acpi_pcihp_pci_status = {
.name = "acpi_pcihp_pci_status",
.version_id = 1,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f59026524f..4f8572eebe 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -361,32 +361,6 @@ static Aml *aml_pci_device_dsm(void)
return method;
}
-static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
-{
- Aml *UUID, *ifctx1;
- uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
-
- aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
- /*
- * PCI Firmware Specification 3.1
- * 4.6. _DSM Definitions for PCI
- */
- UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
- ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
- {
- /* call is for unsupported UUID, bail out */
- aml_append(ifctx1, aml_return(retvar));
- }
- aml_append(ctx, ifctx1);
-
- ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
- {
- /* call is for unsupported REV, bail out */
- aml_append(ifctx1, aml_return(retvar));
- }
- aml_append(ctx, ifctx1);
-}
-
static Aml *aml_pci_edsm(void)
{
Aml *method, *ifctx;
@@ -647,96 +621,6 @@ static bool build_append_notification_callback(Aml *parent_scope,
return !!nr_notifiers;
}
-static Aml *aml_pci_pdsm(void)
-{
- Aml *method, *ifctx, *ifctx1;
- Aml *ret = aml_local(0);
- Aml *caps = aml_local(1);
- Aml *acpi_index = aml_local(2);
- Aml *zero = aml_int(0);
- Aml *one = aml_int(1);
- Aml *not_supp = aml_int(0xFFFFFFFF);
- Aml *func = aml_arg(2);
- Aml *params = aml_arg(4);
- Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
- Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
-
- method = aml_method("PDSM", 5, AML_SERIALIZED);
-
- /* get supported functions */
- ifctx = aml_if(aml_equal(func, zero));
- {
- build_append_pci_dsm_func0_common(ifctx, ret);
-
- aml_append(ifctx, aml_store(zero, caps));
- aml_append(ifctx,
- aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
- /*
- * advertise function 7 if device has acpi-index
- * acpi_index values:
- * 0: not present (default value)
- * FFFFFFFF: not supported (old QEMU without PIDX reg)
- * other: device's acpi-index
- */
- ifctx1 = aml_if(aml_lnot(
- aml_or(aml_equal(acpi_index, zero),
- aml_equal(acpi_index, not_supp), NULL)
- ));
- {
- /* have supported functions */
- aml_append(ifctx1, aml_or(caps, one, caps));
- /* support for function 7 */
- aml_append(ifctx1,
- aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
- }
- aml_append(ifctx, ifctx1);
-
- aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
- aml_append(ifctx, aml_return(ret));
- }
- aml_append(method, ifctx);
-
- /* handle specific functions requests */
- /*
- * PCI Firmware Specification 3.1
- * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
- * Operating Systems
- */
- ifctx = aml_if(aml_equal(func, aml_int(7)));
- {
- Aml *pkg = aml_package(2);
-
- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
- aml_append(ifctx, aml_store(pkg, ret));
- /*
- * Windows calls func=7 without checking if it's available,
- * as workaround Microsoft has suggested to return invalid for func7
- * Package, so return 2 elements package but only initialize elements
- * when acpi_index is supported and leave them uninitialized, which
- * leads elements to being Uninitialized ObjectType and should trip
- * Windows into discarding result as an unexpected and prevent setting
- * bogus 'PCI Label' on the device.
- */
- ifctx1 = aml_if(aml_lnot(aml_lor(
- aml_equal(acpi_index, zero), aml_equal(acpi_index, not_supp)
- )));
- {
- aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
- /*
- * optional, if not impl. should return null string
- */
- aml_append(ifctx1, aml_store(aml_string("%s", ""),
- aml_index(ret, one)));
- }
- aml_append(ifctx, ifctx1);
-
- aml_append(ifctx, aml_return(ret));
- }
-
- aml_append(method, ifctx);
- return method;
-}
-
/*
* build_prt - Define interrupt routing rules
*
@@ -1227,62 +1111,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
return dev;
}
-static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
-{
- Aml *scope;
- Aml *field;
- Aml *method;
-
- scope = aml_scope("_SB.PCI0");
-
- aml_append(scope,
- aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
- field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
- aml_append(field, aml_named_field("PCIU", 32));
- aml_append(field, aml_named_field("PCID", 32));
- aml_append(scope, field);
-
- aml_append(scope,
- aml_operation_region("SEJ", AML_SYSTEM_IO,
- aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
- field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
- aml_append(field, aml_named_field("B0EJ", 32));
- aml_append(scope, field);
-
- aml_append(scope,
- aml_operation_region("BNMR", AML_SYSTEM_IO,
- aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
- field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
- aml_append(field, aml_named_field("BNUM", 32));
- aml_append(field, aml_named_field("PIDX", 32));
- aml_append(scope, field);
-
- aml_append(scope, aml_mutex("BLCK", 0));
-
- method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
- aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
- aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
- aml_append(method,
- aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
- aml_append(method, aml_release(aml_name("BLCK")));
- aml_append(method, aml_return(aml_int(0)));
- aml_append(scope, method);
-
- method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
- aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
- aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
- aml_append(method,
- aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
- aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
- aml_append(method, aml_release(aml_name("BLCK")));
- aml_append(method, aml_return(aml_local(0)));
- aml_append(scope, method);
-
- aml_append(scope, aml_pci_pdsm());
-
- aml_append(table, scope);
-}
-
static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
{
Aml *if_ctx;
@@ -1394,7 +1222,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dsdt, sb_scope);
if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
- build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
+ build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
build_piix4_pci0_int(dsdt);
} else if (q35) {
@@ -1438,7 +1266,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dsdt, sb_scope);
if (pm->pcihp_bridge_en) {
- build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
+ build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
build_q35_pci0_int(dsdt);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 03/36] hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to acpi_dsdt_add_pci_osc
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
2025-07-14 8:04 ` [PATCH v7 01/36] hw/i386/acpi-build: Make aml_pci_device_dsm() static Eric Auger
2025-07-14 8:04 ` [PATCH v7 02/36] hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 04/36] tests/qtest/bios-tables-test: Prepare for changes in the DSDT table Eric Auger
` (33 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Add a new argument to acpi_dsdt_add_pci_osc to be able to disable
native pci hotplug.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
rfc -> v1:
- updated the "Allow OS control for all 5 features" comment
---
hw/pci-host/gpex-acpi.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 0aba47c71c..f34b7cf25e 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -50,7 +50,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
}
}
-static void acpi_dsdt_add_pci_osc(Aml *dev)
+static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplug)
{
Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
@@ -77,11 +77,12 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
/*
- * Allow OS control for all 5 features:
- * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
+ * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability,
+ * and PCIeHotplug depending on enable_native_pcie_hotplug
*/
- aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
- aml_name("CTRL")));
+ aml_append(ifctx, aml_and(aml_name("CTRL"),
+ aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)),
+ aml_name("CTRL")));
ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
@@ -192,7 +193,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
if (is_cxl) {
build_cxl_osc_method(dev);
} else {
- acpi_dsdt_add_pci_osc(dev);
+ acpi_dsdt_add_pci_osc(dev, true);
}
aml_append(scope, dev);
@@ -267,7 +268,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
- acpi_dsdt_add_pci_osc(dev);
+ acpi_dsdt_add_pci_osc(dev, true);
Aml *dev_res0 = aml_device("%s", "RES0");
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 04/36] tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (2 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 03/36] hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to acpi_dsdt_add_pci_osc Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 05/36] hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation Eric Auger
` (32 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
From: Gustavo Romero <gustavo.romero@linaro.org>
This commit adds DSDT blobs to the whilelist in the prospect to
allow changes in the GPEX _OSC method.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
v3 -> v4:
- add missed tests/data/acpi/riscv64/virt/DSDT
v2 -> v3:
- fix for microvm
---
tests/qtest/bios-tables-test-allowed-diff.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..333e5acf63 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,8 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT",
+"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/aarch64/virt/DSDT.memhp",
+"tests/data/acpi/aarch64/virt/DSDT.pxb",
+"tests/data/acpi/aarch64/virt/DSDT.topology",
+"tests/data/acpi/x86/microvm/DSDT.pcie",
+"tests/data/acpi/riscv64/virt/DSDT",
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 05/36] hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (3 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 04/36] tests/qtest/bios-tables-test: Prepare for changes in the DSDT table Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 06/36] hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property Eric Auger
` (31 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
acpi_dsdt_add_pci_osc() name is confusing as it gives the impression
it appends the _OSC method but in fact it also appends the _DSM method
for the host bridge. Let's split the function into two separate ones
and let them return the method Aml pointer instead. This matches the
way it is done on x86 (build_q35_osc_method). In a subsequent patch
we will replace the gpex method by the q35 implementation that will
become shared between ARM and x86.
acpi_dsdt_add_host_bridge_methods is a new top helper that generates
both the _OSC and _DSM methods.
We take the opportunity to move SUPP and CTRL in the _osc method
that use them.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v2 -> v3:
- moved
aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
into the _osc function. (Jonathan)
hence discarded Gustavo's and Igor's R-bs
---
hw/pci-host/gpex-acpi.c | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index f34b7cf25e..80fc2bf032 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -50,14 +50,12 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
}
}
-static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplug)
+static Aml *build_host_bridge_osc(bool enable_native_pcie_hotplug)
{
- Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
-
- /* Declare an _OSC (OS Control Handoff) method */
- aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
- aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
+ Aml *method, *UUID, *ifctx, *ifctx1, *elsectx;
method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
+ aml_append(method, aml_name_decl("SUPP", aml_int(0)));
+ aml_append(method, aml_name_decl("CTRL", aml_int(0)));
aml_append(method,
aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
@@ -103,9 +101,13 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplug)
aml_name("CDW1")));
aml_append(elsectx, aml_return(aml_arg(3)));
aml_append(method, elsectx);
- aml_append(dev, method);
+ return method;
+}
- method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
+static Aml *build_host_bridge_dsm(void)
+{
+ Aml *method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
+ Aml *UUID, *ifctx, *ifctx1, *buf;
/* PCI Firmware Specification 3.0
* 4.6.1. _DSM for PCI Express Slot Information
@@ -124,7 +126,15 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplug)
byte_list[0] = 0;
buf = aml_buffer(1, byte_list);
aml_append(method, aml_return(buf));
- aml_append(dev, method);
+ return method;
+}
+
+static void acpi_dsdt_add_host_bridge_methods(Aml *dev,
+ bool enable_native_pcie_hotplug)
+{
+ /* Declare an _OSC (OS Control Handoff) method */
+ aml_append(dev, build_host_bridge_osc(enable_native_pcie_hotplug));
+ aml_append(dev, build_host_bridge_dsm());
}
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
@@ -193,7 +203,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
if (is_cxl) {
build_cxl_osc_method(dev);
} else {
- acpi_dsdt_add_pci_osc(dev, true);
+ acpi_dsdt_add_host_bridge_methods(dev, true);
}
aml_append(scope, dev);
@@ -268,7 +278,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
- acpi_dsdt_add_pci_osc(dev, true);
+ acpi_dsdt_add_host_bridge_methods(dev, true);
Aml *dev_res0 = aml_device("%s", "RES0");
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 06/36] hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (4 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 05/36] hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 07/36] hw/pci-host/gpex-acpi: Use GED acpi pcihp property Eric Auger
` (30 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
A new boolean property is introduced. This will be used to turn
ACPI PCI hotplug support. By default it is unset.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/acpi/generic_event_device.h | 2 ++
hw/acpi/generic_event_device.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
index d2dac87b4a..f5ffa67a39 100644
--- a/include/hw/acpi/generic_event_device.h
+++ b/include/hw/acpi/generic_event_device.h
@@ -63,6 +63,7 @@
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/cpu.h"
+#include "hw/acpi/pcihp.h"
#include "qom/object.h"
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -114,6 +115,7 @@ struct AcpiGedState {
MemoryRegion container_memhp;
CPUHotplugState cpuhp_state;
MemoryRegion container_cpuhp;
+ AcpiPciHpState pcihp_state;
GEDState ged_state;
uint32_t ged_event_bitmap;
qemu_irq irq;
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index 7a62f8d5bc..7831db412b 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -318,6 +318,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
static const Property acpi_ged_properties[] = {
DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0),
+ DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, AcpiGedState,
+ pcihp_state.use_acpi_hotplug_bridge, 0),
};
static const VMStateDescription vmstate_memhp_state = {
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 07/36] hw/pci-host/gpex-acpi: Use GED acpi pcihp property
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (5 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 06/36] hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 08/36] hw/i386/acpi-build: Turn build_q35_osc_method into a generic method Eric Auger
` (29 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Retrieve the acpi pcihp property value from the ged. In case this latter
is not set, PCI native hotplug is used on pci0. For expander bridges we
keep pci native hotplug, as done on x86 q35.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v4 -> v5:
- check vms->acpi_dev
v3 -> v4:
- Use object_property_get_bool (Igor)
- rework the commit description (Igor)
v2 -> v3:
- don'use the virt arm machine option anymore.
---
include/hw/pci-host/gpex.h | 1 +
hw/arm/virt-acpi-build.c | 9 +++++++++
hw/pci-host/gpex-acpi.c | 3 ++-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index 84471533af..feaf827474 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -45,6 +45,7 @@ struct GPEXConfig {
MemMapEntry pio;
int irq;
PCIBus *bus;
+ bool pci_native_hotplug;
};
typedef struct GPEXIrq GPEXIrq;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 0dfb8ec2c3..8768d5ce50 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -144,12 +144,21 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
bool cxl_present = false;
PCIBus *bus = vms->bus;
+ bool acpi_pcihp = false;
+
+ if (vms->acpi_dev) {
+ acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
+ ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
+ NULL);
+ }
+
struct GPEXConfig cfg = {
.mmio32 = memmap[VIRT_PCIE_MMIO],
.pio = memmap[VIRT_PCIE_PIO],
.ecam = memmap[ecam_id],
.irq = irq,
.bus = vms->bus,
+ .pci_native_hotplug = !acpi_pcihp,
};
if (vms->highmem_mmio) {
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 80fc2bf032..44737a8d81 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -203,6 +203,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
if (is_cxl) {
build_cxl_osc_method(dev);
} else {
+ /* pxb bridges do not have ACPI PCI Hot-plug enabled */
acpi_dsdt_add_host_bridge_methods(dev, true);
}
@@ -278,7 +279,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
- acpi_dsdt_add_host_bridge_methods(dev, true);
+ acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug);
Aml *dev_res0 = aml_device("%s", "RES0");
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 08/36] hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (6 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 07/36] hw/pci-host/gpex-acpi: Use GED acpi pcihp property Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method Eric Auger
` (28 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
GPEX acpi_dsdt_add_pci_osc() does basically the same as
build_q35_osc_method().
Rename build_q35_osc_method() into build_pci_host_bridge_osc_method()
and move it into hw/acpi/pci.c. In a subsequent patch we will
use this later in place of acpi_dsdt_add_pci_osc().
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v2 -> v3:
- move to hw/acpi/pci.c instead of aml-build.c (Igor)
---
include/hw/acpi/pci.h | 2 ++
hw/acpi/pci.c | 50 +++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 54 ++-----------------------------------------
3 files changed, 54 insertions(+), 52 deletions(-)
diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h
index ab0187a894..8a328b580c 100644
--- a/include/hw/acpi/pci.h
+++ b/include/hw/acpi/pci.h
@@ -42,4 +42,6 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope);
void build_srat_generic_affinity_structures(GArray *table_data);
+Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug);
+
#endif
diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c
index d511a85029..2228f1245e 100644
--- a/hw/acpi/pci.c
+++ b/hw/acpi/pci.c
@@ -301,3 +301,53 @@ void build_srat_generic_affinity_structures(GArray *table_data)
object_child_foreach_recursive(object_get_root(), build_acpi_generic_port,
table_data);
}
+
+Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug)
+{
+ Aml *if_ctx;
+ Aml *if_ctx2;
+ Aml *else_ctx;
+ Aml *method;
+ Aml *a_cwd1 = aml_name("CDW1");
+ Aml *a_ctrl = aml_local(0);
+
+ method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
+ aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ if_ctx = aml_if(aml_equal(
+ aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+
+ aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
+
+ /*
+ * Always allow native PME, AER (no dependencies)
+ * Allow SHPC (PCI bridges can have SHPC controller)
+ * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
+ */
+ aml_append(if_ctx, aml_and(a_ctrl,
+ aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
+ /* Unknown revision */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
+ /* Capabilities bits were masked */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ /* Update DWORD3 in the buffer */
+ aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
+ aml_append(method, if_ctx);
+
+ else_ctx = aml_else();
+ /* Unrecognized UUID */
+ aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
+ aml_append(method, else_ctx);
+
+ aml_append(method, aml_return(aml_arg(3)));
+ return method;
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4f8572eebe..91945f716c 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1111,56 +1111,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
return dev;
}
-static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
-{
- Aml *if_ctx;
- Aml *if_ctx2;
- Aml *else_ctx;
- Aml *method;
- Aml *a_cwd1 = aml_name("CDW1");
- Aml *a_ctrl = aml_local(0);
-
- method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
- aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
-
- if_ctx = aml_if(aml_equal(
- aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
- aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
- aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
-
- aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
-
- /*
- * Always allow native PME, AER (no dependencies)
- * Allow SHPC (PCI bridges can have SHPC controller)
- * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
- */
- aml_append(if_ctx, aml_and(a_ctrl,
- aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
-
- if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
- /* Unknown revision */
- aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
- aml_append(if_ctx, if_ctx2);
-
- if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
- /* Capabilities bits were masked */
- aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
- aml_append(if_ctx, if_ctx2);
-
- /* Update DWORD3 in the buffer */
- aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
- aml_append(method, if_ctx);
-
- else_ctx = aml_else();
- /* Unrecognized UUID */
- aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
- aml_append(method, else_ctx);
-
- aml_append(method, aml_return(aml_arg(3)));
- return method;
-}
-
static void build_acpi0017(Aml *table)
{
Aml *dev, *scope, *method;
@@ -1231,7 +1181,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
- aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
+ aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en));
aml_append(dev, aml_pci_edsm());
aml_append(sb_scope, dev);
if (mcfg_valid) {
@@ -1353,7 +1303,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
/* Expander bridges do not have ACPI PCI Hot-plug enabled */
- aml_append(dev, build_q35_osc_method(true));
+ aml_append(dev, build_pci_host_bridge_osc_method(true));
} else {
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
}
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (7 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 08/36] hw/i386/acpi-build: Turn build_q35_osc_method into a generic method Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-27 11:48 ` Michael Tokarev
2025-07-14 8:04 ` [PATCH v7 10/36] tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change Eric Auger
` (27 subsequent siblings)
36 siblings, 1 reply; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
gpex build_host_bridge_osc() and x86 originated
build_pci_host_bridge_osc_method() are mostly identical.
In GPEX, SUPP is set to CDW2 but is not further used. CTRL
is same as Local0.
So let gpex code reuse build_pci_host_bridge_osc_method()
and remove build_host_bridge_osc().
Also add an imply ACPI_PCI clause along with
PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c
when its dependency is resolved (ie. CONFIG_ACPI_PCI).
This is requested to link qemu-system-mips64el.
The disassembled DSDT difference is given below:
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001A4F (6735)
+ * Length 0x00001A35 (6709)
* Revision 0x02
- * Checksum 0xBF
+ * Checksum 0xDD
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -1849,27 +1849,26 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
- SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
- CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
- CTRL &= 0x1F
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
- If ((CDW3 != CTRL))
+ If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
- CDW3 = CTRL /* \_SB_.PCI0.CTRL */
- Return (Arg3)
+ CDW3 = Local0
}
Else
{
CDW1 |= 0x04
- Return (Arg3)
}
+
+ Return (Arg3)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v3 -> v4:
- Fix link issue:
/usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in function `acpi_dsdt_add_host_bridge_methods':
./hw/pci-host/gpex-acpi.c:83: undefined reference to `build_pci_host_bridge_osc_method'
v1 -> v2:
- move in the dsdt.dsl diff in the commit message and remove useless
info (Gustavo, Michael)
---
hw/pci-host/gpex-acpi.c | 62 ++++-------------------------------------
hw/pci-host/Kconfig | 1 +
2 files changed, 6 insertions(+), 57 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 44737a8d81..952a0ace19 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -1,5 +1,6 @@
#include "qemu/osdep.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/arm/virt.h"
#include "hw/pci/pci_bus.h"
@@ -50,61 +51,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
}
}
-static Aml *build_host_bridge_osc(bool enable_native_pcie_hotplug)
-{
- Aml *method, *UUID, *ifctx, *ifctx1, *elsectx;
- method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
- aml_append(method, aml_name_decl("SUPP", aml_int(0)));
- aml_append(method, aml_name_decl("CTRL", aml_int(0)));
- aml_append(method,
- aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
-
- /* PCI Firmware Specification 3.0
- * 4.5.1. _OSC Interface for PCI Host Bridge Devices
- * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
- * identified by the Universal Unique IDentifier (UUID)
- * 33DB4D5B-1FF7-401C-9657-7441C03DD766
- */
- UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
- ifctx = aml_if(aml_equal(aml_arg(0), UUID));
- aml_append(ifctx,
- aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
- aml_append(ifctx,
- aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
- aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
- aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
-
- /*
- * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability,
- * and PCIeHotplug depending on enable_native_pcie_hotplug
- */
- aml_append(ifctx, aml_and(aml_name("CTRL"),
- aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)),
- aml_name("CTRL")));
-
- ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
- aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
- aml_name("CDW1")));
- aml_append(ifctx, ifctx1);
-
- ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
- aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
- aml_name("CDW1")));
- aml_append(ifctx, ifctx1);
-
- aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
- aml_append(ifctx, aml_return(aml_arg(3)));
- aml_append(method, ifctx);
-
- elsectx = aml_else();
- aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
- aml_name("CDW1")));
- aml_append(elsectx, aml_return(aml_arg(3)));
- aml_append(method, elsectx);
- return method;
-}
-
-static Aml *build_host_bridge_dsm(void)
+static Aml *build_pci_host_bridge_dsm_method(void)
{
Aml *method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
Aml *UUID, *ifctx, *ifctx1, *buf;
@@ -133,8 +80,9 @@ static void acpi_dsdt_add_host_bridge_methods(Aml *dev,
bool enable_native_pcie_hotplug)
{
/* Declare an _OSC (OS Control Handoff) method */
- aml_append(dev, build_host_bridge_osc(enable_native_pcie_hotplug));
- aml_append(dev, build_host_bridge_dsm());
+ aml_append(dev,
+ build_pci_host_bridge_osc_method(enable_native_pcie_hotplug));
+ aml_append(dev, build_pci_host_bridge_dsm_method());
}
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 35c0415242..9824fa188d 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -54,6 +54,7 @@ config PCI_EXPRESS_Q35
config PCI_EXPRESS_GENERIC_BRIDGE
bool
select PCI_EXPRESS
+ imply ACPI_PCI
config PCI_EXPRESS_XILINX
bool
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-14 8:04 ` [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method Eric Auger
@ 2025-07-27 11:48 ` Michael Tokarev
2025-07-28 9:07 ` Michael Tokarev
0 siblings, 1 reply; 52+ messages in thread
From: Michael Tokarev @ 2025-07-27 11:48 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
On 14.07.2025 11:04, Eric Auger wrote:
> gpex build_host_bridge_osc() and x86 originated
> build_pci_host_bridge_osc_method() are mostly identical.
>
> In GPEX, SUPP is set to CDW2 but is not further used. CTRL
> is same as Local0.
>
> So let gpex code reuse build_pci_host_bridge_osc_method()
> and remove build_host_bridge_osc().
>
> Also add an imply ACPI_PCI clause along with
> PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c
> when its dependency is resolved (ie. CONFIG_ACPI_PCI).
> This is requested to link qemu-system-mips64el.
This patch somehow broke microvm-only build which is used
by debian.
configure options used (trimmed a bit):
../configure \
--without-default-features \
--target-list=x86_64-softmmu \
--enable-kvm --disable-tcg \
--enable-pixman \
--enable-vnc \
--audio-drv-list="" \
--without-default-devices \
--with-devices-x86_64=microvm \
--enable-vhost-user
configs/devices/x86_64-softmmu/microvm.mak:
---- cut ----
# see configs/devices/i386-softmmu/default.mak
# for additional devices which can be disabled
#
CONFIG_PCI_DEVICES=n
CONFIG_MICROVM=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_SERIAL=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_INPUT_HOST=y
CONFIG_VHOST_USER_INPUT=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_SCSI=y
CONFIG_VIRTIO_RNG=y
CONFIG_VIRTIO_CRYPTO=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_GPU=y
CONFIG_VHOST_USER_GPU=y
---- cut ----
The result:
FAILED: qemu-system-x86_64
cc -m64 @qemu-system-x86_64.rsp
/usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in function
`acpi_dsdt_add_host_bridge_methods':
hw/pci-host/gpex-acpi.c:83:(.text+0x274): undefined reference to
`build_pci_host_bridge_osc_method'
collect2: error: ld returned 1 exit status
Is it because my devices file wrong now, or some `select FOO` kconfig
is missing?
Should this code be enabled with this configuration anyway?
Thanks,
/mjt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-27 11:48 ` Michael Tokarev
@ 2025-07-28 9:07 ` Michael Tokarev
2025-07-28 14:56 ` Eric Auger
0 siblings, 1 reply; 52+ messages in thread
From: Michael Tokarev @ 2025-07-28 9:07 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl, Gerd Hoffmann
Cc: pbonzini, philmd, alex.bennee
On 27.07.2025 14:48, Michael Tokarev wrote:
> On 14.07.2025 11:04, Eric Auger wrote:
>> gpex build_host_bridge_osc() and x86 originated
>> build_pci_host_bridge_osc_method() are mostly identical.
>>
>> In GPEX, SUPP is set to CDW2 but is not further used. CTRL is
>> same as Local0.
>>
>> So let gpex code reuse build_pci_host_bridge_osc_method() and
>> remove build_host_bridge_osc().
>>
>> Also add an imply ACPI_PCI clause along with
>> PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its
>> dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested
>> to link qemu-system-mips64el.
>
> This patch somehow broke microvm-only build which is used by debian.
>
> configure options used (trimmed a bit):
>
> ../configure \ --without-default-features \ --target-list=x86_64-
> softmmu \ --enable-kvm --disable-tcg \ --enable-pixman \ --enable-
> vnc \ --audio-drv-list="" \ --without-default-devices \ --with-
> devices-x86_64=microvm \ --enable-vhost-user
>
> configs/devices/x86_64-softmmu/microvm.mak: ---- cut ---- # see
> configs/devices/i386-softmmu/default.mak # for additional devices
> which can be disabled # CONFIG_PCI_DEVICES=n
>
> CONFIG_MICROVM=y
>
> CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_SERIAL=y CONFIG_VIRTIO_INPUT=y
> CONFIG_VIRTIO_INPUT_HOST=y CONFIG_VHOST_USER_INPUT=y
> CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_SCSI=y CONFIG_VIRTIO_RNG=y
> CONFIG_VIRTIO_CRYPTO=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_GPU=y
> CONFIG_VHOST_USER_GPU=y ---- cut ----
>
> The result: FAILED: qemu-system-x86_64 cc -m64 @qemu-system-
> x86_64.rsp /usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in
> function `acpi_dsdt_add_host_bridge_methods': hw/pci-host/gpex-
> acpi.c:83:(.text+0x274): undefined reference to
> `build_pci_host_bridge_osc_method' collect2: error: ld returned 1
> exit status
In hw/i386/Kconfig, MICROVM selects ACPI_HW_REDUCED (not ACPI or
ACPI_PCI), *and* PCI_EXPRESS_GENERIC_BRIDGE. But in hw/pci/meson.build,
pci.c (where the function in question is defined) is built when
ACPI_PCI is enabled. Something's not right here.
Addig kraxel for 24db877ab6e6 "microvm: add pcie support".
Thanks
/mjt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-28 9:07 ` Michael Tokarev
@ 2025-07-28 14:56 ` Eric Auger
2025-07-28 15:17 ` Michael Tokarev
2025-08-01 12:29 ` Michael S. Tsirkin
0 siblings, 2 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-28 14:56 UTC (permalink / raw)
To: Michael Tokarev, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, Jonathan.Cameron, gustavo.romero,
anisinha, mst, shannon.zhaosl, Gerd Hoffmann
Cc: pbonzini, philmd, alex.bennee
Hi Michael,
On 7/28/25 11:07 AM, Michael Tokarev wrote:
> On 27.07.2025 14:48, Michael Tokarev wrote:
>> On 14.07.2025 11:04, Eric Auger wrote:
>>> gpex build_host_bridge_osc() and x86 originated
>>> build_pci_host_bridge_osc_method() are mostly identical.
>>>
>>> In GPEX, SUPP is set to CDW2 but is not further used. CTRL is
>>> same as Local0.
>>>
>>> So let gpex code reuse build_pci_host_bridge_osc_method() and remove
>>> build_host_bridge_osc().
>>>
>>> Also add an imply ACPI_PCI clause along with
>>> PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its
>>> dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested
>>> to link qemu-system-mips64el.
>>
>> This patch somehow broke microvm-only build which is used by debian.
>>
>> configure options used (trimmed a bit):
>>
>> ../configure \ --without-default-features \ --target-list=x86_64-
>> softmmu \ --enable-kvm --disable-tcg \ --enable-pixman \ --enable-
>> vnc \ --audio-drv-list="" \ --without-default-devices \ --with-
>> devices-x86_64=microvm \ --enable-vhost-user
>>
>> configs/devices/x86_64-softmmu/microvm.mak: ---- cut ---- # see
>> configs/devices/i386-softmmu/default.mak # for additional devices
>> which can be disabled # CONFIG_PCI_DEVICES=n
>>
>> CONFIG_MICROVM=y
>>
>> CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_SERIAL=y CONFIG_VIRTIO_INPUT=y
>> CONFIG_VIRTIO_INPUT_HOST=y CONFIG_VHOST_USER_INPUT=y
>> CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_SCSI=y CONFIG_VIRTIO_RNG=y
>> CONFIG_VIRTIO_CRYPTO=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_GPU=y
>> CONFIG_VHOST_USER_GPU=y ---- cut ----
>>
>> The result: FAILED: qemu-system-x86_64 cc -m64 @qemu-system-
>> x86_64.rsp /usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in
>> function `acpi_dsdt_add_host_bridge_methods': hw/pci-host/gpex-
>> acpi.c:83:(.text+0x274): undefined reference to
>> `build_pci_host_bridge_osc_method' collect2: error: ld returned 1
>> exit status
>
> In hw/i386/Kconfig, MICROVM selects ACPI_HW_REDUCED (not ACPI or
> ACPI_PCI), *and* PCI_EXPRESS_GENERIC_BRIDGE. But in hw/pci/meson.build,
> pci.c (where the function in question is defined) is built when
> ACPI_PCI is enabled. Something's not right here.
This commit added an imply ACPI_PCI to the PCI_EXPRESS_GENERIC_BRIDGE
config in hw/pci-host/Kconfig:
config PCI_EXPRESS_GENERIC_BRIDGE
bool
select PCI_EXPRESS -> selects PCI
imply ACPI_PCI
In hw/acpi/Kconfig we have:
config ACPI_PCI
bool
depends on ACPI && PCI
ACPI is selected by ACPI_HW_REDUCED
config ACPI_HW_REDUCED
bool
select ACPI
select ACPI_MEMORY_HOTPLUG
select ACPI_NVDIMM
so logically the ACPI && PCI dependencies for ACPI_PCI should be
resolved. What do I miss?
regards
Eric
>
> Addig kraxel for 24db877ab6e6 "microvm: add pcie support".
>
> Thanks
>
> /mjt
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-28 14:56 ` Eric Auger
@ 2025-07-28 15:17 ` Michael Tokarev
2025-07-28 15:29 ` Michael Tokarev
2025-07-28 15:34 ` Eric Auger
2025-08-01 12:29 ` Michael S. Tsirkin
1 sibling, 2 replies; 52+ messages in thread
From: Michael Tokarev @ 2025-07-28 15:17 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl, Gerd Hoffmann
Cc: pbonzini, philmd, alex.bennee
On 28.07.2025 17:56, Eric Auger wrote:
> Hi Michael,
Hi!
> This commit added an imply ACPI_PCI to the PCI_EXPRESS_GENERIC_BRIDGE
> config in hw/pci-host/Kconfig:
>
> config PCI_EXPRESS_GENERIC_BRIDGE
> bool
> select PCI_EXPRESS -> selects PCI
> imply ACPI_PCI
>
> In hw/acpi/Kconfig we have:
>
> config ACPI_PCI
> bool
> depends on ACPI && PCI
>
> ACPI is selected by ACPI_HW_REDUCED
>
> config ACPI_HW_REDUCED
> bool
> select ACPI
> select ACPI_MEMORY_HOTPLUG
> select ACPI_NVDIMM
>
> so logically the ACPI && PCI dependencies for ACPI_PCI should be
> resolved. What do I miss?
I think it should be "select" not "imply", which seems to be stricter.
With a devices file like I'm using - it looks like - only things which
are selected gets enabled. But this commit brings hard dependency
between the bridge device and ACPI_PCI, as demonstrated by my example.
So when the bridge selects ACPI_PCI instead of implying it, whole thing
works (I just verified it)
I wonder why we build microvm-only executable in debian... Initially
it was a small binary aimed at very fast startup and light runtime.
But with time it grew quite a lot of things...
Thanks,
/mjt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-28 15:17 ` Michael Tokarev
@ 2025-07-28 15:29 ` Michael Tokarev
2025-07-28 15:34 ` Eric Auger
1 sibling, 0 replies; 52+ messages in thread
From: Michael Tokarev @ 2025-07-28 15:29 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl, Gerd Hoffmann
Cc: pbonzini, philmd, alex.bennee
On 28.07.2025 18:17, Michael Tokarev wrote:
> I think it should be "select" not "imply", which seems to be stricter.
> With a devices file like I'm using - it looks like - only things which
> are selected gets enabled. But this commit brings hard dependency
> between the bridge device and ACPI_PCI, as demonstrated by my example.
> So when the bridge selects ACPI_PCI instead of implying it, whole thing
> works (I just verified it)
I just sent a patch doing exactly that.
Alternatively this can be #ifdef ACPI_PCI in the code, - I dunno if
that's possible now.
Thanks,
/mjt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-28 15:17 ` Michael Tokarev
2025-07-28 15:29 ` Michael Tokarev
@ 2025-07-28 15:34 ` Eric Auger
1 sibling, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-28 15:34 UTC (permalink / raw)
To: Michael Tokarev, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, Jonathan.Cameron, gustavo.romero,
anisinha, mst, shannon.zhaosl, Gerd Hoffmann
Cc: pbonzini, philmd, alex.bennee
Hi Michael,
On 7/28/25 5:17 PM, Michael Tokarev wrote:
> On 28.07.2025 17:56, Eric Auger wrote:
>> Hi Michael,
>
> Hi!
>
>> This commit added an imply ACPI_PCI to the PCI_EXPRESS_GENERIC_BRIDGE
>> config in hw/pci-host/Kconfig:
>>
>> config PCI_EXPRESS_GENERIC_BRIDGE
>> bool
>> select PCI_EXPRESS -> selects PCI
>> imply ACPI_PCI
>>
>> In hw/acpi/Kconfig we have:
>>
>> config ACPI_PCI
>> bool
>> depends on ACPI && PCI
>>
>> ACPI is selected by ACPI_HW_REDUCED
>>
>> config ACPI_HW_REDUCED
>> bool
>> select ACPI
>> select ACPI_MEMORY_HOTPLUG
>> select ACPI_NVDIMM
>>
>> so logically the ACPI && PCI dependencies for ACPI_PCI should be
>> resolved. What do I miss?
>
> I think it should be "select" not "imply", which seems to be stricter.
> With a devices file like I'm using - it looks like - only things which
> are selected gets enabled. But this commit brings hard dependency
> between the bridge device and ACPI_PCI, as demonstrated by my example.
> So when the bridge selects ACPI_PCI instead of implying it, whole thing
> works (I just verified it)
build_pci_host_bridge_osc_method() is called from gpex-acpi.c
pci_ss.add(when: ['CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', 'CONFIG_ACPI'],
if_true: files('gpex-acpi.c'))
so the hard dependency exists only if ACPI is selected.
If you use "select" you will force ACPI_PCI even if ACPI is not set
which does not sound what we want?
regards
Eric
>
> I wonder why we build microvm-only executable in debian... Initially
> it was a small binary aimed at very fast startup and light runtime.
> But with time it grew quite a lot of things...
>
> Thanks,
>
> /mjt
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-07-28 14:56 ` Eric Auger
2025-07-28 15:17 ` Michael Tokarev
@ 2025-08-01 12:29 ` Michael S. Tsirkin
2025-08-03 16:49 ` Eric Auger
1 sibling, 1 reply; 52+ messages in thread
From: Michael S. Tsirkin @ 2025-08-01 12:29 UTC (permalink / raw)
To: Eric Auger
Cc: Michael Tokarev, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, Jonathan.Cameron, gustavo.romero,
anisinha, shannon.zhaosl, Gerd Hoffmann, pbonzini, philmd,
alex.bennee
On Mon, Jul 28, 2025 at 04:56:37PM +0200, Eric Auger wrote:
> Hi Michael,
>
> On 7/28/25 11:07 AM, Michael Tokarev wrote:
> > On 27.07.2025 14:48, Michael Tokarev wrote:
> >> On 14.07.2025 11:04, Eric Auger wrote:
> >>> gpex build_host_bridge_osc() and x86 originated
> >>> build_pci_host_bridge_osc_method() are mostly identical.
> >>>
> >>> In GPEX, SUPP is set to CDW2 but is not further used. CTRL is
> >>> same as Local0.
> >>>
> >>> So let gpex code reuse build_pci_host_bridge_osc_method() and remove
> >>> build_host_bridge_osc().
> >>>
> >>> Also add an imply ACPI_PCI clause along with
> >>> PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its
> >>> dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested
> >>> to link qemu-system-mips64el.
> >>
> >> This patch somehow broke microvm-only build which is used by debian.
> >>
> >> configure options used (trimmed a bit):
> >>
> >> ../configure \ --without-default-features \ --target-list=x86_64-
> >> softmmu \ --enable-kvm --disable-tcg \ --enable-pixman \ --enable-
> >> vnc \ --audio-drv-list="" \ --without-default-devices \ --with-
> >> devices-x86_64=microvm \ --enable-vhost-user
> >>
> >> configs/devices/x86_64-softmmu/microvm.mak: ---- cut ---- # see
> >> configs/devices/i386-softmmu/default.mak # for additional devices
> >> which can be disabled # CONFIG_PCI_DEVICES=n
> >>
> >> CONFIG_MICROVM=y
> >>
> >> CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_SERIAL=y CONFIG_VIRTIO_INPUT=y
> >> CONFIG_VIRTIO_INPUT_HOST=y CONFIG_VHOST_USER_INPUT=y
> >> CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_SCSI=y CONFIG_VIRTIO_RNG=y
> >> CONFIG_VIRTIO_CRYPTO=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_GPU=y
> >> CONFIG_VHOST_USER_GPU=y ---- cut ----
> >>
> >> The result: FAILED: qemu-system-x86_64 cc -m64 @qemu-system-
> >> x86_64.rsp /usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in
> >> function `acpi_dsdt_add_host_bridge_methods': hw/pci-host/gpex-
> >> acpi.c:83:(.text+0x274): undefined reference to
> >> `build_pci_host_bridge_osc_method' collect2: error: ld returned 1
> >> exit status
> >
> > In hw/i386/Kconfig, MICROVM selects ACPI_HW_REDUCED (not ACPI or
> > ACPI_PCI), *and* PCI_EXPRESS_GENERIC_BRIDGE. But in hw/pci/meson.build,
> > pci.c (where the function in question is defined) is built when
> > ACPI_PCI is enabled. Something's not right here.
> This commit added an imply ACPI_PCI to the PCI_EXPRESS_GENERIC_BRIDGE
> config in hw/pci-host/Kconfig:
>
> config PCI_EXPRESS_GENERIC_BRIDGE
> bool
> select PCI_EXPRESS -> selects PCI
> imply ACPI_PCI
>
> In hw/acpi/Kconfig we have:
>
> config ACPI_PCI
> bool
> depends on ACPI && PCI
>
> ACPI is selected by ACPI_HW_REDUCED
>
> config ACPI_HW_REDUCED
> bool
> select ACPI
> select ACPI_MEMORY_HOTPLUG
> select ACPI_NVDIMM
>
> so logically the ACPI && PCI dependencies for ACPI_PCI should be
> resolved. What do I miss?
> regards
>
> Eric
>
Not sure I get what are you proposing?
>
>
>
>
>
>
>
> >
> > Addig kraxel for 24db877ab6e6 "microvm: add pcie support".
> >
> > Thanks
> >
> > /mjt
> >
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-08-01 12:29 ` Michael S. Tsirkin
@ 2025-08-03 16:49 ` Eric Auger
2025-08-04 6:29 ` Michael Tokarev
0 siblings, 1 reply; 52+ messages in thread
From: Eric Auger @ 2025-08-03 16:49 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Michael Tokarev, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, Jonathan.Cameron, gustavo.romero,
anisinha, shannon.zhaosl, Gerd Hoffmann, pbonzini, philmd,
alex.bennee
Hi Michael,
On 8/1/25 2:29 PM, Michael S. Tsirkin wrote:
> On Mon, Jul 28, 2025 at 04:56:37PM +0200, Eric Auger wrote:
>> Hi Michael,
>>
>> On 7/28/25 11:07 AM, Michael Tokarev wrote:
>>> On 27.07.2025 14:48, Michael Tokarev wrote:
>>>> On 14.07.2025 11:04, Eric Auger wrote:
>>>>> gpex build_host_bridge_osc() and x86 originated
>>>>> build_pci_host_bridge_osc_method() are mostly identical.
>>>>>
>>>>> In GPEX, SUPP is set to CDW2 but is not further used. CTRL is
>>>>> same as Local0.
>>>>>
>>>>> So let gpex code reuse build_pci_host_bridge_osc_method() and remove
>>>>> build_host_bridge_osc().
>>>>>
>>>>> Also add an imply ACPI_PCI clause along with
>>>>> PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its
>>>>> dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested
>>>>> to link qemu-system-mips64el.
>>>> This patch somehow broke microvm-only build which is used by debian.
>>>>
>>>> configure options used (trimmed a bit):
>>>>
>>>> ../configure \ --without-default-features \ --target-list=x86_64-
>>>> softmmu \ --enable-kvm --disable-tcg \ --enable-pixman \ --enable-
>>>> vnc \ --audio-drv-list="" \ --without-default-devices \ --with-
>>>> devices-x86_64=microvm \ --enable-vhost-user
>>>>
>>>> configs/devices/x86_64-softmmu/microvm.mak: ---- cut ---- # see
>>>> configs/devices/i386-softmmu/default.mak # for additional devices
>>>> which can be disabled # CONFIG_PCI_DEVICES=n
>>>>
>>>> CONFIG_MICROVM=y
>>>>
>>>> CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_SERIAL=y CONFIG_VIRTIO_INPUT=y
>>>> CONFIG_VIRTIO_INPUT_HOST=y CONFIG_VHOST_USER_INPUT=y
>>>> CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_SCSI=y CONFIG_VIRTIO_RNG=y
>>>> CONFIG_VIRTIO_CRYPTO=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_GPU=y
>>>> CONFIG_VHOST_USER_GPU=y ---- cut ----
>>>>
>>>> The result: FAILED: qemu-system-x86_64 cc -m64 @qemu-system-
>>>> x86_64.rsp /usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in
>>>> function `acpi_dsdt_add_host_bridge_methods': hw/pci-host/gpex-
>>>> acpi.c:83:(.text+0x274): undefined reference to
>>>> `build_pci_host_bridge_osc_method' collect2: error: ld returned 1
>>>> exit status
>>> In hw/i386/Kconfig, MICROVM selects ACPI_HW_REDUCED (not ACPI or
>>> ACPI_PCI), *and* PCI_EXPRESS_GENERIC_BRIDGE. But in hw/pci/meson.build,
>>> pci.c (where the function in question is defined) is built when
>>> ACPI_PCI is enabled. Something's not right here.
>> This commit added an imply ACPI_PCI to the PCI_EXPRESS_GENERIC_BRIDGE
>> config in hw/pci-host/Kconfig:
>>
>> config PCI_EXPRESS_GENERIC_BRIDGE
>> bool
>> select PCI_EXPRESS -> selects PCI
>> imply ACPI_PCI
>>
>> In hw/acpi/Kconfig we have:
>>
>> config ACPI_PCI
>> bool
>> depends on ACPI && PCI
>>
>> ACPI is selected by ACPI_HW_REDUCED
>>
>> config ACPI_HW_REDUCED
>> bool
>> select ACPI
>> select ACPI_MEMORY_HOTPLUG
>> select ACPI_NVDIMM
>>
>> so logically the ACPI && PCI dependencies for ACPI_PCI should be
>> resolved. What do I miss?
>> regards
>>
>> Eric
>>
>
> Not sure I get what are you proposing?
I have not proposed anything ;-) - sorry I am on vacation - I was trying
to enumerate the various config settings and to me dependencies should
be resolved so I fail to understand. Unfortunately I cannot test because
the problem happens with a custom microvm.mak. I would need this latter
to reproduce and try to fix.
if the microvm.mak selects PCI_EXPRESS_GENERIC_BRIDGE (which selects
PCI_EXPRESS which itself selects PCI) and ACPI_HW_REDUCED (which selects
ACPI), the imply ACPI_PCI should end up as a selection because PCI and
ACPI are resolved. At least that's my understanding. Reading it again,
please can you check whether ACPI_HW_REDUCED is selected *before*
PCI_EXPRESS_GENERIC_BRIDGE in the custom microvm.mak. Depending on the
order of dependency resolution it might make a difference. Otherwise
please can you send the full microvm.mak and configure command so that I
can try reproducing. Thanks Eric
>
>>
>>
>>
>>
>>
>>
>>> Addig kraxel for 24db877ab6e6 "microvm: add pcie support".
>>>
>>> Thanks
>>>
>>> /mjt
>>>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-08-03 16:49 ` Eric Auger
@ 2025-08-04 6:29 ` Michael Tokarev
2025-08-04 15:27 ` Eric Auger
0 siblings, 1 reply; 52+ messages in thread
From: Michael Tokarev @ 2025-08-04 6:29 UTC (permalink / raw)
To: eric.auger, Michael S. Tsirkin
Cc: eric.auger.pro, qemu-devel, qemu-arm, peter.maydell, imammedo,
Jonathan.Cameron, gustavo.romero, anisinha, shannon.zhaosl,
Gerd Hoffmann, pbonzini, philmd, alex.bennee
On 03.08.2025 19:49, Eric Auger wrote:
...
> I have not proposed anything ;-) - sorry I am on vacation - I was trying
> to enumerate the various config settings and to me dependencies should
> be resolved so I fail to understand. Unfortunately I cannot test because
> the problem happens with a custom microvm.mak. I would need this latter
> to reproduce and try to fix.
>
> if the microvm.mak selects PCI_EXPRESS_GENERIC_BRIDGE (which selects
> PCI_EXPRESS which itself selects PCI) and ACPI_HW_REDUCED (which selects
> ACPI), the imply ACPI_PCI should end up as a selection because PCI and
> ACPI are resolved. At least that's my understanding. Reading it again,
> please can you check whether ACPI_HW_REDUCED is selected *before*
> PCI_EXPRESS_GENERIC_BRIDGE in the custom microvm.mak. Depending on the
> order of dependency resolution it might make a difference. Otherwise
> please can you send the full microvm.mak and configure command so that I
> can try reproducing. Thanks Eric
All the details were in my very first reply to the original patch:
https://lore.kernel.org/qemu-devel/ddf6f9e3-daaa-4ea1-a5e6-d402a75524c8@tls.msk.ru/
Thanks,
/mjt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
2025-08-04 6:29 ` Michael Tokarev
@ 2025-08-04 15:27 ` Eric Auger
0 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-08-04 15:27 UTC (permalink / raw)
To: Michael Tokarev, Michael S. Tsirkin
Cc: eric.auger.pro, qemu-devel, qemu-arm, peter.maydell, imammedo,
Jonathan.Cameron, gustavo.romero, anisinha, shannon.zhaosl,
Gerd Hoffmann, pbonzini, philmd, alex.bennee
Hi Michael,
On 8/4/25 8:29 AM, Michael Tokarev wrote:
> On 03.08.2025 19:49, Eric Auger wrote:
> ...
>> I have not proposed anything ;-) - sorry I am on vacation - I was trying
>> to enumerate the various config settings and to me dependencies should
>> be resolved so I fail to understand. Unfortunately I cannot test because
>> the problem happens with a custom microvm.mak. I would need this latter
>> to reproduce and try to fix.
>>
>> if the microvm.mak selects PCI_EXPRESS_GENERIC_BRIDGE (which selects
>> PCI_EXPRESS which itself selects PCI) and ACPI_HW_REDUCED (which selects
>> ACPI), the imply ACPI_PCI should end up as a selection because PCI and
>> ACPI are resolved. At least that's my understanding. Reading it again,
>> please can you check whether ACPI_HW_REDUCED is selected *before*
>> PCI_EXPRESS_GENERIC_BRIDGE in the custom microvm.mak. Depending on the
>> order of dependency resolution it might make a difference. Otherwise
>> please can you send the full microvm.mak and configure command so that I
>> can try reproducing. Thanks Eric
>
> All the details were in my very first reply to the original patch:
> https://lore.kernel.org/qemu-devel/ddf6f9e3-daaa-4ea1-a5e6-d402a75524c8@tls.msk.ru/
>
Sorry I was confused by the fact the microvm.mak was not upstream and
its content was cut in your original report.
I was able to reproduce and could check that both ACPI and PCI are set
since objects that depend on them are compiled. However
ACPI_PCI which depend on both and which is implied by
PCI_EXPRESS_GENERIC_BRIDGE is not set as opposed to what I would have
expected.
So I sent "[PATCH for 10.1] microvm: Explicitly select ACPI_PCI" as a
tentative fix of your issue. It looks similar to PC setup. An
alternative could be to set it in your .mak file.
Nevetheless I still fail to understand what prevents the imply from
beeing active as a select here. Maybe that's due to the "eveythning
unset by default".
Thanks
Eric
>
> Thanks,
>
> /mjt
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v7 10/36] tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (8 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 09/36] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 11/36] hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper Eric Auger
` (26 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Update the reference DSDT blobs after GPEX _OSC change. The _OSC change
affects the aarch64 'virt' and the x86 'microvm' machines.
DSDT diff is the same for all the machines/tests:
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001A4F (6735)
+ * Length 0x00001A35 (6709)
* Revision 0x02
- * Checksum 0xBF
+ * Checksum 0xDD
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -1849,27 +1849,26 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
- SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
- CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
- CTRL &= 0x1F
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
- If ((CDW3 != CTRL))
+ If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
- CDW3 = CTRL /* \_SB_.PCI0.CTRL */
- Return (Arg3)
+ CDW3 = Local0
}
Else
{
CDW1 |= 0x04
- Return (Arg3)
}
+
+ Return (Arg3)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v3 -> v4
- fix the commit msg: dsl reverse diff (Jonathan)
---
tests/qtest/bios-tables-test-allowed-diff.h | 7 -------
tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5158 bytes
.../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5244 bytes
tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6519 bytes
tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7603 bytes
tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5360 bytes
tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
8 files changed, 7 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 333e5acf63..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,8 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT",
-"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/DSDT.memhp",
-"tests/data/acpi/aarch64/virt/DSDT.pxb",
-"tests/data/acpi/aarch64/virt/DSDT.topology",
-"tests/data/acpi/x86/microvm/DSDT.pcie",
-"tests/data/acpi/riscv64/virt/DSDT",
diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/virt/DSDT
index 36d3e5d5a5e47359b6dcb3706f98b4f225677591..acab6e65febbc210158d4c39be0680bbb90250f5 100644
GIT binary patch
delta 114
zcmX@3u}p)@CD<iIO@x7g>C8kfX{JVpjp}Y(OkR^V=X2?C2#NTx$NL96vvg%MIJ<-!
zF7RWWyjw`i#5kckflEGNfxx86nT)j{87>a6yzr#S&Mx7`2@o*>kXS(iNMs?;W@BMV
FMgSUfAKd@|
delta 152
zcmZ3caYlp7CD<jzM}&caNqQoeG*i3NMs+tXCWon;^SSgm<T!#u0|FR0oI`?q7)0DS
z<Nbr3S-P?roL#~V7kIEwUN5BOX9QAG;Or7^3{q7MBDmy1<N|?7lQS7>L29`;z&gYx
bO@^t12n&FO3qXoN;!Cm@@@?i7mSh9~5Tq&5
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt
index e6154d0355f84fdcc51387b4db8f9ee63acae4e9..54c27e7d95b4956ed1b5dee0d299ccb08dc2a73e 100644
GIT binary patch
delta 114
zcmZ3a`A37xCD<jTMudTZsdFNiG*i3lM)f&dOkR^VALY{H5EAiWkM|FDX6ediaCQkd
zT;Rt#Sx{KZ#5kckflEGNfxx86nT)j{87>a6yzr#S&Mx7`2@o*>kXS(iNMs?;=1yTr
FMgUJNAb|h?
delta 152
zcmeyPu}G84CD<iokq83=(~XH-(oDVX8`bA<F*!`#e3VO%LyjXjG$4S1!#O0#he5=R
zGu}VgnWZb6!PzC;aDfN=WL9A<KO>Nm0%w<SW00z95Wyu6A{Piunw-g43sTF)0oEZl
bX);V5L|6bMTmVuG5?_+NkZ*Icup}b@<J&8B
diff --git a/tests/data/acpi/aarch64/virt/DSDT.memhp b/tests/data/acpi/aarch64/virt/DSDT.memhp
index 33f011d6b635035a04c0b39ce9b4e219f7ae74b7..4330bc97cba0950191c45ac833533db7a190db81 100644
GIT binary patch
delta 114
zcmbPh{N0GlCD<jTT#|u->Fq==X{M&B8`a&on7k%!&gatO5EAiWkM|FDX6ediaCQkd
zT;Rt#dAE?3iE%=80+)Qk0)a`BGZ||^GF%*BdErTuon69>6Ch#&AhCi3kjO%w&Bnr6
FYyg6XAvXX3
delta 152
zcmexvG}oBRCD<iot|S8klg&gfX{L_p8`a&om>i~V&gatOkmCpr4G3W1a1IIbVGwcS
zjQ0<AX6ediaCQkdT;RbzdA*R9pAkq&fwN1vF-TQ4h~Sb3kqZPSP0nPj1*zrY0P7H&
bG#RE2A}jzBE&wS8i7&}s$hVnSIExJcpiV0*
diff --git a/tests/data/acpi/aarch64/virt/DSDT.pxb b/tests/data/acpi/aarch64/virt/DSDT.pxb
index c0fdc6e9c1396cc2259dc4bc665ba023adcf4c9b..7fdbc03e2bf9fb7d35704779253de36e362f0bf9 100644
GIT binary patch
delta 207
zcmexwz1f<}CD<iovn&Gx)9r~|(oB6fHmbXEG5NM`&ga^|E+pc^9`7IQ%+i(3;Or7^
zxWJEfa-NKqiE%=80+)Qk0)a`BGZ||^GF%*BdErTuon69>6Ch#&AhCi3kjO%w$<JhL
aH-8e+V`TE0v{^|+kAs?qZ+<2t$p`>t?mg51
delta 282
zcmdmN{ok6)CD<k8zbpd-Q^!OuX{N5b8`a&on4CK{=W}gfm*WTy4G3W1a1IIbVGwcS
zjQ0<AX6ediaCQkdT;Rbz*-%K!&j_TXz}Y3-7^JEiL~zN2$OQtECTB9%g4A+xfOUvX
unhaA15f%Um7l0Il#Fu0*<lEdYl+DQGFm>}EVLcA|TR*v9$aeB|nL7Yd7E^Zs
diff --git a/tests/data/acpi/aarch64/virt/DSDT.topology b/tests/data/acpi/aarch64/virt/DSDT.topology
index 029d03eecc4efddc001e5377e85ac8e831294362..969b4f6560d3ae39f5b7e0064b7122905476fce8 100644
GIT binary patch
delta 114
zcmbQH^+A)%CD<k8g9rly)24}B(oEex8`TB4nY<=#w&d315EAiWkM|FDX6ediaCQkd
zT;Rt#xm8%p#5kckflEGNfxx86nT)j{87>a6yzr#S&Mx7`2@o*>kXS(iNMs?;=D)&{
Fi~vUbAmso6
delta 152
zcmeyMIZcbpCD<iIOq79viGL!OG*hGhMs)#hCWon;ExGkL<T!#u0|FR0oI`?q7)0DS
z<Nbr3S-P?roL#~V7kIEwt`yetGXg0oaCQkd2C1qB5nS>ha)H34$(f9`Ahlc^U>#zU
bCd1T0gatst1t7&B@g>;{`8Hn{mSh9~yBaCk
diff --git a/tests/data/acpi/riscv64/virt/DSDT b/tests/data/acpi/riscv64/virt/DSDT
index 6a33f5647ddd6de3a0f000f718b58f6fff44f0fd..527f239dab13a00ad42e5a70b8dc2b89f12aa84a 100644
GIT binary patch
delta 113
zcmew%eMy?jCD<k85-$S-lgdOcX(r!W8`WD`nA|39UdN)vAtd6%9`7IQ%+i(3;Or7^
zxWJEf@;4qW6XS&H1TMLR1p<>MXEN4;WVkrM^1_oQJG+D%CqTpmKw<?6Ad!VUlk<4H
E0ByV>p#T5?
delta 151
zcmca4{X?3|CD<k82QLEyQ_(~&X(s2p8`WD`n0%&eUdN)vA;%FM8W6z1;T#g=!yw|u
z8SfwL%+i(3;Or7^xWI#b@+%%KKO>Nm0%w<SW00z95Wyu6A{Piunw-g43sTF)0oEZl
aX);V5L|6bMTmVuG5?_+NkZ-aFZx;X$O)QlF
diff --git a/tests/data/acpi/x86/microvm/DSDT.pcie b/tests/data/acpi/x86/microvm/DSDT.pcie
index 8eacd21d6ecdf9a3cd3e4f03cf1b40748dcbf53e..ba258f454dc0e59ef2fd67e0ce37e270e7c122e8 100644
GIT binary patch
delta 113
zcmX>vzEYgaCD<ioB{u^D)Axy7(oD|VH>#&HG5Ji`+{YxqAtd6%9`7IQ%+i(3;Or7^
zxWJEf@*XZN6XS&H1TMLR1p<>MXEN4;WVkrM^1_oQJG+D%CqTpmKw<?6Ad!VUlTEm1
F0{}^9AprmY
delta 151
zcmZ1}eqNl*CD<k8JU0Ualj}q-X(rE|8`V>pn4BhW?qd?*kmCpr4G3W1a1IIbVGwcS
zjQ0<AX6ediaCQkdT;Rbzc>|Z0pAkq&fwN1vF-TQ4h~Sb3kqZPSP0nPj1*zrY0P7H&
aG#RE2A}jzBE&wS8i7&}s$Tyjfdo}=5#47aw
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 11/36] hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (9 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 10/36] tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 12/36] hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug Eric Auger
` (25 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Extract the code that reserves resources for ACPI PCI hotplug
into a new helper named build_append_pcihp_resources() and
move it to pcihp.c. We will reuse it on ARM.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v2 -> v3:
- fixed indent (Jonathan)
---
include/hw/acpi/pcihp.h | 2 ++
hw/acpi/pcihp.c | 18 ++++++++++++++++++
hw/i386/acpi-build.c | 15 ++-------------
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 971451e8ea..8a46a414cc 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -75,6 +75,8 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,
void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr);
void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar);
+void build_append_pcihp_resources(Aml *table,
+ uint64_t io_addr, uint64_t io_len);
/* Called on reset */
void acpi_pcihp_reset(AcpiPciHpState *s);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index cbe7e01385..5ca36c8619 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -685,6 +685,24 @@ void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
aml_append(table, scope);
}
+/* Reserve PCIHP resources */
+void build_append_pcihp_resources(Aml *scope /* \\_SB.PCI0 */,
+ uint64_t io_addr, uint64_t io_len)
+{
+ Aml *dev, *crs;
+
+ dev = aml_device("PHPR");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
+ aml_append(dev,
+ aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, io_addr, io_addr, 1, io_len));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
const VMStateDescription vmstate_acpi_pcihp_pci_status = {
.name = "acpi_pcihp_pci_status",
.version_id = 1,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 91945f716c..52cef834ed 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1432,19 +1432,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
/* reserve PCIHP resources */
if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
- dev = aml_device("PHPR");
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
- aml_append(dev,
- aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
- /* device present, functioning, decoding, not shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
- crs = aml_resource_template();
- aml_append(crs,
- aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
- pm->pcihp_io_len)
- );
- aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(scope, dev);
+ build_append_pcihp_resources(scope,
+ pm->pcihp_io_base, pm->pcihp_io_len);
}
aml_append(dsdt, scope);
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 12/36] hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (10 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 11/36] hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 13/36] hw/i386/acpi-build: Move build_append_notification_callback to pcihp Eric Auger
` (24 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
On ARM we will put the operation regions in AML_SYSTEM_MEMORY.
So let's allow this configuration.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
include/hw/acpi/pcihp.h | 3 ++-
hw/acpi/pcihp.c | 8 ++++----
hw/i386/acpi-build.c | 4 ++--
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 8a46a414cc..253ac6e483 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -28,6 +28,7 @@
#define HW_ACPI_PCIHP_H
#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
#include "hw/hotplug.h"
#define ACPI_PCIHP_IO_BASE_PROP "acpi-pcihp-io-base"
@@ -73,7 +74,7 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,
AcpiPciHpState *s, DeviceState *dev,
Error **errp);
-void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr);
+void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs, uint64_t pcihp_addr);
void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar);
void build_append_pcihp_resources(Aml *table,
uint64_t io_addr, uint64_t io_len);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 5ca36c8619..afa3ec5f4d 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -629,7 +629,7 @@ static Aml *aml_pci_pdsm(void)
return method;
}
-void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
+void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs, uint64_t pcihp_addr)
{
Aml *scope;
Aml *field;
@@ -638,21 +638,21 @@ void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
scope = aml_scope("_SB.PCI0");
aml_append(scope,
- aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
+ aml_operation_region("PCST", rs, aml_int(pcihp_addr), 0x08));
field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
aml_append(field, aml_named_field("PCIU", 32));
aml_append(field, aml_named_field("PCID", 32));
aml_append(scope, field);
aml_append(scope,
- aml_operation_region("SEJ", AML_SYSTEM_IO,
+ aml_operation_region("SEJ", rs,
aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
aml_append(field, aml_named_field("B0EJ", 32));
aml_append(scope, field);
aml_append(scope,
- aml_operation_region("BNMR", AML_SYSTEM_IO,
+ aml_operation_region("BNMR", rs,
aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
aml_append(field, aml_named_field("BNUM", 32));
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 52cef834ed..6ca2b34ef8 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1172,7 +1172,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dsdt, sb_scope);
if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
- build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
+ build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
}
build_piix4_pci0_int(dsdt);
} else if (q35) {
@@ -1216,7 +1216,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dsdt, sb_scope);
if (pm->pcihp_bridge_en) {
- build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
+ build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
}
build_q35_pci0_int(dsdt);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 13/36] hw/i386/acpi-build: Move build_append_notification_callback to pcihp
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (11 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 12/36] hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 14/36] hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots " Eric Auger
` (23 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
We plan to reuse build_append_notification_callback() on ARM
so let's move it to pcihp.c.
No functional change intended.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
include/hw/acpi/pcihp.h | 1 +
hw/acpi/pcihp.c | 58 +++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 58 -----------------------------------------
3 files changed, 59 insertions(+), 58 deletions(-)
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 253ac6e483..f4fd44cb32 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -78,6 +78,7 @@ void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs, uint64_t pcihp_addr);
void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar);
void build_append_pcihp_resources(Aml *table,
uint64_t io_addr, uint64_t io_len);
+bool build_append_notification_callback(Aml *parent_scope, const PCIBus *bus);
/* Called on reset */
void acpi_pcihp_reset(AcpiPciHpState *s);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index afa3ec5f4d..b64d06afc9 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -39,6 +39,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qom/qom-qobject.h"
+#include "qobject/qnum.h"
#include "trace.h"
#define ACPI_PCIHP_SIZE 0x0018
@@ -703,6 +704,63 @@ void build_append_pcihp_resources(Aml *scope /* \\_SB.PCI0 */,
aml_append(scope, dev);
}
+bool build_append_notification_callback(Aml *parent_scope, const PCIBus *bus)
+{
+ Aml *method;
+ PCIBus *sec;
+ QObject *bsel;
+ int nr_notifiers = 0;
+ GQueue *pcnt_bus_list = g_queue_new();
+
+ QLIST_FOREACH(sec, &bus->child, sibling) {
+ Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
+ if (pci_bus_is_root(sec)) {
+ continue;
+ }
+ nr_notifiers = nr_notifiers +
+ build_append_notification_callback(br_scope, sec);
+ /*
+ * add new child scope to parent
+ * and keep track of bus that have PCNT,
+ * bus list is used later to call children PCNTs from this level PCNT
+ */
+ if (nr_notifiers) {
+ g_queue_push_tail(pcnt_bus_list, sec);
+ aml_append(parent_scope, br_scope);
+ }
+ }
+
+ /*
+ * Append PCNT method to notify about events on local and child buses.
+ * ps: hostbridge might not have hotplug (bsel) enabled but might have
+ * child bridges that do have bsel.
+ */
+ method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
+
+ /* If bus supports hotplug select it and notify about local events */
+ bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
+ if (bsel) {
+ uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+
+ aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
+ aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
+ aml_int(1))); /* Device Check */
+ aml_append(method, aml_call2("DVNT", aml_name("PCID"),
+ aml_int(3))); /* Eject Request */
+ nr_notifiers++;
+ }
+
+ /* Notify about child bus events in any case */
+ while ((sec = g_queue_pop_head(pcnt_bus_list))) {
+ aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
+ }
+
+ aml_append(parent_scope, method);
+ qobject_unref(bsel);
+ g_queue_free(pcnt_bus_list);
+ return !!nr_notifiers;
+}
+
const VMStateDescription vmstate_acpi_pcihp_pci_status = {
.name = "acpi_pcihp_pci_status",
.version_id = 1,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6ca2b34ef8..3275675e60 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -563,64 +563,6 @@ void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
}
}
-static bool build_append_notification_callback(Aml *parent_scope,
- const PCIBus *bus)
-{
- Aml *method;
- PCIBus *sec;
- QObject *bsel;
- int nr_notifiers = 0;
- GQueue *pcnt_bus_list = g_queue_new();
-
- QLIST_FOREACH(sec, &bus->child, sibling) {
- Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
- if (pci_bus_is_root(sec)) {
- continue;
- }
- nr_notifiers = nr_notifiers +
- build_append_notification_callback(br_scope, sec);
- /*
- * add new child scope to parent
- * and keep track of bus that have PCNT,
- * bus list is used later to call children PCNTs from this level PCNT
- */
- if (nr_notifiers) {
- g_queue_push_tail(pcnt_bus_list, sec);
- aml_append(parent_scope, br_scope);
- }
- }
-
- /*
- * Append PCNT method to notify about events on local and child buses.
- * ps: hostbridge might not have hotplug (bsel) enabled but might have
- * child bridges that do have bsel.
- */
- method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
-
- /* If bus supports hotplug select it and notify about local events */
- bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
- if (bsel) {
- uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
-
- aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
- aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
- aml_int(1))); /* Device Check */
- aml_append(method, aml_call2("DVNT", aml_name("PCID"),
- aml_int(3))); /* Eject Request */
- nr_notifiers++;
- }
-
- /* Notify about child bus events in any case */
- while ((sec = g_queue_pop_head(pcnt_bus_list))) {
- aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
- }
-
- aml_append(parent_scope, method);
- qobject_unref(bsel);
- g_queue_free(pcnt_bus_list);
- return !!nr_notifiers;
-}
-
/*
* build_prt - Define interrupt routing rules
*
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 14/36] hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to pcihp
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (12 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 13/36] hw/i386/acpi-build: Move build_append_notification_callback to pcihp Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:04 ` [PATCH v7 15/36] hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info Eric Auger
` (22 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
We intend to reuse build_append_pci_bus_devices and build_append_pcihp_slots
on ARM. So let's move them to hw/acpi/pcihp.c as well as all static
helpers they use.
No functional change intended.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v2 -> v3:
- changed the layout of the commit message
- reordered the moved functions to match the original ordering
(Jonathan)
---
include/hw/acpi/pci.h | 1 -
include/hw/acpi/pcihp.h | 2 +
hw/acpi/pcihp.c | 173 ++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 172 ---------------------------------------
4 files changed, 175 insertions(+), 173 deletions(-)
diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h
index 8a328b580c..69bae95eac 100644
--- a/include/hw/acpi/pci.h
+++ b/include/hw/acpi/pci.h
@@ -37,7 +37,6 @@ typedef struct AcpiMcfgInfo {
void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info,
const char *oem_id, const char *oem_table_id);
-void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus);
void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope);
void build_srat_generic_affinity_structures(GArray *table_data);
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index f4fd44cb32..5506a58862 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -80,6 +80,8 @@ void build_append_pcihp_resources(Aml *table,
uint64_t io_addr, uint64_t io_len);
bool build_append_notification_callback(Aml *parent_scope, const PCIBus *bus);
+void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus);
+
/* Called on reset */
void acpi_pcihp_reset(AcpiPciHpState *s);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index b64d06afc9..2c76edeb15 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,6 +27,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/pcihp.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
#include "hw/pci-host/i440fx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
@@ -761,6 +762,178 @@ bool build_append_notification_callback(Aml *parent_scope, const PCIBus *bus)
return !!nr_notifiers;
}
+static Aml *aml_pci_device_dsm(void)
+{
+ Aml *method;
+
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ {
+ Aml *params = aml_local(0);
+ Aml *pkg = aml_package(2);
+ aml_append(pkg, aml_int(0));
+ aml_append(pkg, aml_int(0));
+ aml_append(method, aml_store(pkg, params));
+ aml_append(method,
+ aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
+ aml_append(method,
+ aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
+ aml_append(method,
+ aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3), params))
+ );
+ }
+ return method;
+}
+
+static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
+{
+ Aml *method;
+
+ g_assert(pdev->acpi_index != 0);
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ {
+ Aml *params = aml_local(0);
+ Aml *pkg = aml_package(1);
+ aml_append(pkg, aml_int(pdev->acpi_index));
+ aml_append(method, aml_store(pkg, params));
+ aml_append(method,
+ aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3), params))
+ );
+ }
+ return method;
+}
+
+static void build_append_pcihp_notify_entry(Aml *method, int slot)
+{
+ Aml *if_ctx;
+ int32_t devfn = PCI_DEVFN(slot, 0);
+
+ if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
+ aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
+ aml_append(method, if_ctx);
+}
+
+static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
+{
+ const PCIDevice *pdev = bus->devices[devfn];
+
+ if (PCI_FUNC(devfn)) {
+ if (IS_PCI_BRIDGE(pdev)) {
+ /*
+ * Ignore only hotplugged PCI bridges on !0 functions, but
+ * allow describing cold plugged bridges on all functions
+ */
+ if (DEVICE(pdev)->hotplugged) {
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
+static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
+{
+ PCIDevice *pdev = bus->devices[devfn];
+ if (pdev) {
+ return is_devfn_ignored_generic(devfn, bus) ||
+ !DEVICE_GET_CLASS(pdev)->hotpluggable ||
+ /* Cold plugged bridges aren't themselves hot-pluggable */
+ (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
+ } else { /* non populated slots */
+ /*
+ * hotplug is supported only for non-multifunction device
+ * so generate device description only for function 0
+ */
+ if (PCI_FUNC(devfn) ||
+ (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
+{
+ int devfn;
+ Aml *dev, *notify_method = NULL, *method;
+ QObject *bsel = object_property_get_qobject(OBJECT(bus),
+ ACPI_PCIHP_PROP_BSEL, NULL);
+ uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+ qobject_unref(bsel);
+
+ aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
+ notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
+
+ for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
+ int slot = PCI_SLOT(devfn);
+ int adr = slot << 16 | PCI_FUNC(devfn);
+
+ if (is_devfn_ignored_hotplug(devfn, bus)) {
+ continue;
+ }
+
+ if (bus->devices[devfn]) {
+ dev = aml_scope("S%.02X", devfn);
+ } else {
+ dev = aml_device("S%.02X", devfn);
+ aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
+ }
+
+ /*
+ * Can't declare _SUN here for every device as it changes 'slot'
+ * enumeration order in linux kernel, so use another variable for it
+ */
+ aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
+ aml_append(dev, aml_pci_device_dsm());
+
+ aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
+ /* add _EJ0 to make slot hotpluggable */
+ method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+ aml_append(method,
+ aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
+ );
+ aml_append(dev, method);
+
+ build_append_pcihp_notify_entry(notify_method, slot);
+
+ /* device descriptor has been composed, add it into parent context */
+ aml_append(parent_scope, dev);
+ }
+ aml_append(parent_scope, notify_method);
+}
+
+void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
+{
+ int devfn;
+ Aml *dev;
+
+ for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
+ /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
+ int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
+ PCIDevice *pdev = bus->devices[devfn];
+
+ if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
+ continue;
+ }
+
+ /* start to compose PCI device descriptor */
+ dev = aml_device("S%.02X", devfn);
+ aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
+
+ call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
+ /* add _DSM if device has acpi-index set */
+ if (pdev->acpi_index &&
+ !object_property_get_bool(OBJECT(pdev), "hotpluggable",
+ &error_abort)) {
+ aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
+ }
+
+ /* device descriptor has been composed, add it into parent context */
+ aml_append(parent_scope, dev);
+ }
+}
+
const VMStateDescription vmstate_acpi_pcihp_pci_status = {
.name = "acpi_pcihp_pci_status",
.version_id = 1,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 3275675e60..fe8bc62c03 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -338,29 +338,6 @@ build_facs(GArray *table_data)
g_array_append_vals(table_data, reserved, 40); /* Reserved */
}
-static Aml *aml_pci_device_dsm(void)
-{
- Aml *method;
-
- method = aml_method("_DSM", 4, AML_SERIALIZED);
- {
- Aml *params = aml_local(0);
- Aml *pkg = aml_package(2);
- aml_append(pkg, aml_int(0));
- aml_append(pkg, aml_int(0));
- aml_append(method, aml_store(pkg, params));
- aml_append(method,
- aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
- aml_append(method,
- aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
- aml_append(method,
- aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
- aml_arg(2), aml_arg(3), params))
- );
- }
- return method;
-}
-
static Aml *aml_pci_edsm(void)
{
Aml *method, *ifctx;
@@ -414,155 +391,6 @@ static Aml *aml_pci_edsm(void)
return method;
}
-static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
-{
- Aml *method;
-
- g_assert(pdev->acpi_index != 0);
- method = aml_method("_DSM", 4, AML_SERIALIZED);
- {
- Aml *params = aml_local(0);
- Aml *pkg = aml_package(1);
- aml_append(pkg, aml_int(pdev->acpi_index));
- aml_append(method, aml_store(pkg, params));
- aml_append(method,
- aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
- aml_arg(2), aml_arg(3), params))
- );
- }
- return method;
-}
-
-static void build_append_pcihp_notify_entry(Aml *method, int slot)
-{
- Aml *if_ctx;
- int32_t devfn = PCI_DEVFN(slot, 0);
-
- if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
- aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
- aml_append(method, if_ctx);
-}
-
-static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
-{
- const PCIDevice *pdev = bus->devices[devfn];
-
- if (PCI_FUNC(devfn)) {
- if (IS_PCI_BRIDGE(pdev)) {
- /*
- * Ignore only hotplugged PCI bridges on !0 functions, but
- * allow describing cold plugged bridges on all functions
- */
- if (DEVICE(pdev)->hotplugged) {
- return true;
- }
- }
- }
- return false;
-}
-
-static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
-{
- PCIDevice *pdev = bus->devices[devfn];
- if (pdev) {
- return is_devfn_ignored_generic(devfn, bus) ||
- !DEVICE_GET_CLASS(pdev)->hotpluggable ||
- /* Cold plugged bridges aren't themselves hot-pluggable */
- (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
- } else { /* non populated slots */
- /*
- * hotplug is supported only for non-multifunction device
- * so generate device description only for function 0
- */
- if (PCI_FUNC(devfn) ||
- (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
- return true;
- }
- }
- return false;
-}
-
-void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
-{
- int devfn;
- Aml *dev, *notify_method = NULL, *method;
- QObject *bsel = object_property_get_qobject(OBJECT(bus),
- ACPI_PCIHP_PROP_BSEL, NULL);
- uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
- qobject_unref(bsel);
-
- aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
- notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
-
- for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
- int slot = PCI_SLOT(devfn);
- int adr = slot << 16 | PCI_FUNC(devfn);
-
- if (is_devfn_ignored_hotplug(devfn, bus)) {
- continue;
- }
-
- if (bus->devices[devfn]) {
- dev = aml_scope("S%.02X", devfn);
- } else {
- dev = aml_device("S%.02X", devfn);
- aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
- }
-
- /*
- * Can't declare _SUN here for every device as it changes 'slot'
- * enumeration order in linux kernel, so use another variable for it
- */
- aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
- aml_append(dev, aml_pci_device_dsm());
-
- aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
- /* add _EJ0 to make slot hotpluggable */
- method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
- aml_append(method,
- aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
- );
- aml_append(dev, method);
-
- build_append_pcihp_notify_entry(notify_method, slot);
-
- /* device descriptor has been composed, add it into parent context */
- aml_append(parent_scope, dev);
- }
- aml_append(parent_scope, notify_method);
-}
-
-void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
-{
- int devfn;
- Aml *dev;
-
- for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
- /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
- int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
- PCIDevice *pdev = bus->devices[devfn];
-
- if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
- continue;
- }
-
- /* start to compose PCI device descriptor */
- dev = aml_device("S%.02X", devfn);
- aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
-
- call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
- /* add _DSM if device has acpi-index set */
- if (pdev->acpi_index &&
- !object_property_get_bool(OBJECT(pdev), "hotpluggable",
- &error_abort)) {
- aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
- }
-
- /* device descriptor has been composed, add it into parent context */
- aml_append(parent_scope, dev);
- }
-}
-
/*
* build_prt - Define interrupt routing rules
*
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 15/36] hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (13 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 14/36] hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots " Eric Auger
@ 2025-07-14 8:04 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 16/36] hw/i386/acpi-build: Move aml_pci_edsm to a generic place Eric Auger
` (21 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:04 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
pcihp acpi_set_pci_info() generic code currently uses
acpi_get_i386_pci_host() to retrieve the pci host bridge.
To make it work also on ARM we get rid of that call and
directly use AcpiPciHpState::root.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v2 -> v3:
- Use AcpiPciHpState::root
v1 -> v2
- described the fact we changed the implementation of
acpi_get_pci_host() in the commit msg.
---
hw/acpi/pcihp.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 2c76edeb15..2db2f16940 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -99,10 +99,10 @@ static void *acpi_set_bsel(PCIBus *bus, void *opaque)
return info;
}
-static void acpi_set_pci_info(bool has_bridge_hotplug)
+static void acpi_set_pci_info(AcpiPciHpState *s)
{
static bool bsel_is_set;
- Object *host = acpi_get_i386_pci_host();
+ bool has_bridge_hotplug = s->use_acpi_hotplug_bridge;
PCIBus *bus;
BSELInfo info = { .bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT,
.has_bridge_hotplug = has_bridge_hotplug };
@@ -112,11 +112,8 @@ static void acpi_set_pci_info(bool has_bridge_hotplug)
}
bsel_is_set = true;
- if (!host) {
- return;
- }
- bus = PCI_HOST_BRIDGE(host)->bus;
+ bus = s->root;
if (bus) {
/* Scan all PCI buses. Set property to enable acpi based hotplug. */
pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &info);
@@ -266,7 +263,7 @@ static void acpi_pcihp_update(AcpiPciHpState *s)
void acpi_pcihp_reset(AcpiPciHpState *s)
{
- acpi_set_pci_info(s->use_acpi_hotplug_bridge);
+ acpi_set_pci_info(s);
acpi_pcihp_update(s);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 16/36] hw/i386/acpi-build: Move aml_pci_edsm to a generic place
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (14 preceding siblings ...)
2025-07-14 8:04 ` [PATCH v7 15/36] hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 17/36] qtest/bios-tables-test: Prepare for fixing the aarch64 viot test Eric Auger
` (20 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Move aml_pci_edsm to pci-bridge.c since we want to reuse that for
ARM and acpi-index support. Also rename it into build_pci_bridge_edsm.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v3->v4:
- renamed into build_pci_bridge_edsm() (Jonathan, Igor)
v2 -> v3:
- move to pci-bridge.c instead of pcihp.c (Igor)
---
include/hw/acpi/pci.h | 1 +
hw/acpi/pci-bridge.c | 54 ++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 57 ++-----------------------------------------
3 files changed, 57 insertions(+), 55 deletions(-)
diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h
index 69bae95eac..20b672575f 100644
--- a/include/hw/acpi/pci.h
+++ b/include/hw/acpi/pci.h
@@ -42,5 +42,6 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope);
void build_srat_generic_affinity_structures(GArray *table_data);
Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug);
+Aml *build_pci_bridge_edsm(void);
#endif
diff --git a/hw/acpi/pci-bridge.c b/hw/acpi/pci-bridge.c
index 7baa7034a1..394a919479 100644
--- a/hw/acpi/pci-bridge.c
+++ b/hw/acpi/pci-bridge.c
@@ -35,3 +35,57 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope)
}
}
}
+
+Aml *build_pci_bridge_edsm(void)
+{
+ Aml *method, *ifctx;
+ Aml *zero = aml_int(0);
+ Aml *func = aml_arg(2);
+ Aml *ret = aml_local(0);
+ Aml *aidx = aml_local(1);
+ Aml *params = aml_arg(4);
+
+ method = aml_method("EDSM", 5, AML_SERIALIZED);
+
+ /* get supported functions */
+ ifctx = aml_if(aml_equal(func, zero));
+ {
+ /* 1: have supported functions */
+ /* 7: support for function 7 */
+ const uint8_t caps = 1 | BIT(7);
+ build_append_pci_dsm_func0_common(ifctx, ret);
+ aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
+ aml_append(ifctx, aml_return(ret));
+ }
+ aml_append(method, ifctx);
+
+ /* handle specific functions requests */
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
+ * Operating Systems
+ */
+ ifctx = aml_if(aml_equal(func, aml_int(7)));
+ {
+ Aml *pkg = aml_package(2);
+ aml_append(pkg, zero);
+ /* optional, if not impl. should return null string */
+ aml_append(pkg, aml_string("%s", ""));
+ aml_append(ifctx, aml_store(pkg, ret));
+
+ /*
+ * IASL is fine when initializing Package with computational data,
+ * however it makes guest unhappy /it fails to process such AML/.
+ * So use runtime assignment to set acpi-index after initializer
+ * to make OSPM happy.
+ */
+ aml_append(ifctx,
+ aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
+ aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
+ aml_append(ifctx, aml_return(ret));
+ }
+ aml_append(method, ifctx);
+
+ return method;
+}
+
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fe8bc62c03..423c4959fe 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -338,59 +338,6 @@ build_facs(GArray *table_data)
g_array_append_vals(table_data, reserved, 40); /* Reserved */
}
-static Aml *aml_pci_edsm(void)
-{
- Aml *method, *ifctx;
- Aml *zero = aml_int(0);
- Aml *func = aml_arg(2);
- Aml *ret = aml_local(0);
- Aml *aidx = aml_local(1);
- Aml *params = aml_arg(4);
-
- method = aml_method("EDSM", 5, AML_SERIALIZED);
-
- /* get supported functions */
- ifctx = aml_if(aml_equal(func, zero));
- {
- /* 1: have supported functions */
- /* 7: support for function 7 */
- const uint8_t caps = 1 | BIT(7);
- build_append_pci_dsm_func0_common(ifctx, ret);
- aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
- aml_append(ifctx, aml_return(ret));
- }
- aml_append(method, ifctx);
-
- /* handle specific functions requests */
- /*
- * PCI Firmware Specification 3.1
- * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
- * Operating Systems
- */
- ifctx = aml_if(aml_equal(func, aml_int(7)));
- {
- Aml *pkg = aml_package(2);
- aml_append(pkg, zero);
- /* optional, if not impl. should return null string */
- aml_append(pkg, aml_string("%s", ""));
- aml_append(ifctx, aml_store(pkg, ret));
-
- /*
- * IASL is fine when initializing Package with computational data,
- * however it makes guest unhappy /it fails to process such AML/.
- * So use runtime assignment to set acpi-index after initializer
- * to make OSPM happy.
- */
- aml_append(ifctx,
- aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
- aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
- aml_append(ifctx, aml_return(ret));
- }
- aml_append(method, ifctx);
-
- return method;
-}
-
/*
* build_prt - Define interrupt routing rules
*
@@ -937,7 +884,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
dev = aml_device("PCI0");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
- aml_append(dev, aml_pci_edsm());
+ aml_append(dev, build_pci_bridge_edsm());
aml_append(sb_scope, dev);
aml_append(dsdt, sb_scope);
@@ -952,7 +899,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en));
- aml_append(dev, aml_pci_edsm());
+ aml_append(dev, build_pci_bridge_edsm());
aml_append(sb_scope, dev);
if (mcfg_valid) {
aml_append(sb_scope, build_q35_dram_controller(&mcfg));
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 17/36] qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (15 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 16/36] hw/i386/acpi-build: Move aml_pci_edsm to a generic place Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 18/36] qtest/bios-tables-test: Add a variant to " Eric Auger
` (19 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
The test misses a variant and this puts the mess on subsequent
rebuild-expected-aml.sh where a first DSDT reference blob is
overriden by another one.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/aarch64/virt/DSDT.viot | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7a74beab3d 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT.viot",
diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch64/virt/DSDT.viot
new file mode 100644
index 0000000000..e69de29bb2
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 18/36] qtest/bios-tables-test: Add a variant to the aarch64 viot test
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (16 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 17/36] qtest/bios-tables-test: Prepare for fixing the aarch64 viot test Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 19/36] qtest/bios-tables-test: Generate DSDT.viot Eric Auger
` (18 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 4dbc07ec5e..357bcefd37 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2237,6 +2237,7 @@ static void test_acpi_aarch64_virt_viot(void)
test_data data = {
.machine = "virt",
.arch = "aarch64",
+ .variant = ".viot",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 19/36] qtest/bios-tables-test: Generate DSDT.viot
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (17 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 18/36] qtest/bios-tables-test: Add a variant to " Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 20/36] tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT table Eric Auger
` (17 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Use a specific DSDT.viot reference blob instead of relying on
the default DSDT blob. The content is unchanged.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5158 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 7a74beab3d..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT.viot",
diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch64/virt/DSDT.viot
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..acab6e65febbc210158d4c39be0680bbb90250f5 100644
GIT binary patch
literal 5158
zcmZvg%WoT16o=2)6MH;<Wc*0%I8N+Bsd!dnyJ^zWmfB+{aj_HQNgE_rawJql$)*w&
zQmK&AELzBpMq(YL{vk-LkXW!|(KQ?X0d^SOc{t~%o>|y)ALqOG8=sMmZ^!NIT`CYo
z{%G$y+itD>`OvA=YBi0B)V=z)p54~&Pu%uod|Y;H+cqZKy-vF2412b1uahyk+w0Ky
z_`0(@2**Z)ZQHKbgE3>`jNEM5EIv<=0w%~J`Y}eDc7ceV(D-;`bKlwYxu10hcWv8l
zkTG%hT4vIiI8ICR5m__iBO-}X5ZTi2jlwPUcSgImZLgg#JBvJD+@wgbxXlrDe|1Et
zW#2$V7@{5^+G-aK31LPghRzrb&S;8^sKkgdMw2tHhzwm~7>sd+GuA}LoWw90V~sPe
zij0`VNHNA$&R7>2afy*(jCIb~5E+KVuoz>5Gp>n@gv7`(#x=&M2QLSvm}yFk0%Kg~
z3^7gdB?(h~kug5z3^`9z(mqOzaf37DJWWfCGGpB23^`9T5~IQxw>U%2(|L)p${3$;
zhMcFC#HcaGZO)MMG%GRQVvH7N$a$KR7#A6%%^7l@<|W1@#&8&;A?Im9V!X>39nO&R
zbU|Xg&lp|Kkn?m=VtmLLo17u%X;ETaW{fS)kn^-8F>J=z<_tMcmn24mF?yUK=V@7D
zTw#nmoFV7wvc$N`7@u;6oTn9uvB4O9&XDtTMPgiMi~(ab<vd-L7&jPWhco0ntxAkr
zjIkRqdU}6W5Dj;RwqtM3ijU#Q&1TG`SLeL#&G(BK>?_13?#R`~J}TG_pfm$e7X_5x
zH$&Y~y9(YOK&fJcZ|fa_<@X^gc#Dt~Mb;&O<@cSlUJjjJ@T)0S%id7Wq}K^rO;z)C
zx5${Z+dH%8=<bcORkJcAhkEpYYGhN5I`n|PrHAwdJs?sLuS^?`_VWF2%%faVPfn+#
zejD=dwZ3iFDVI|HW<))nuo3Osc9U{xJvE(bq+;r`mWpanF5{1Ran19linN2d5ihba
zYpKX^YQ&GUgUASZk>M&)FEZRg)Qb$KM*YZo5E=C&!&P)IGTedgMTS##KQi3B?nj2J
z%z@_|c+R2coF5sk5(Cc|c*f8(hMsZojDu$!J>%$UfTsbT26`IknE=lOcqY&@fu1IK
zn&4@or-`0P@Jxbd5<QdXnF7xgc&5-Zg`R2fOoL|{J=5r!0nZG0X3#T(p7Y>251#Yr
zIgg$ecv|3Tp{IqOS@6t)XBIuP=$Ql09C+r?Gl!me@XUi}9zFBuSpd%hcoxvJfSwEB
zxd5IE=(&KNi{QBko{Q+Yh@M68EP`hdJ&WjB0?!h7me8|=o=f1l1fEOixrCl&@GOI8
z89mGBxeT7m;JJ*R%jj7F&kA@}(6fS`E8w{To-63Nf}X43xeA`E=(&oXRq(8WXB9oG
zp=ZIGIPDg_%BWKx_5a4NShnNl;~&x#Ns+py>O*@`Buc5n9CcaK>3`~PnHs(PqDWdQ
z>bHod-t_4$B8^TyU@_ix<jt7+lh~#DpHQJ6pX|DhesV}oXTN^7Gk5w`Hg8(v!RzL~
z)ynOk_aC=@z4_OdCx@o)boLu3ho<3l_M4B?$HCJBvwCo5y*z!WeXqj3vHDs5<*7I9
z_gQM>(ShpuCFOT1RQ=Uq;iE~%9q4Bl{5Ahv|NU=w?YqHG#eW7%zd3`m#Oc@cDjU@_
z^+Ds~fj;WGthjN!BP@0B)imul%)O^OoldLjDYMH`_v%Ef9lw8Bow;pwI}`ux!9Q@T
zt0L)cuan;DcA%h)YVY}>N8M3(i&8{J!qmsllB(%+-EO~DSebP1?Ij+m#=)6&`t-n5
ZwaN40{-|vpjgObqjlY;*>N!CX_CM8!>@ENR
literal 0
HcmV?d00001
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 20/36] tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT table
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (18 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 19/36] qtest/bios-tables-test: Generate DSDT.viot Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 21/36] hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index Eric Auger
` (16 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
From: Gustavo Romero <gustavo.romero@linaro.org>
This commit adds DSDT blobs to the whilelist in the prospect to
allow changes in the arm virt DSDT method.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..023fbc6059 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,7 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT",
+"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/aarch64/virt/DSDT.memhp",
+"tests/data/acpi/aarch64/virt/DSDT.pxb",
+"tests/data/acpi/aarch64/virt/DSDT.topology",
+"tests/data/acpi/aarch64/virt/DSDT.viot",
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 21/36] hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (19 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 20/36] tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT table Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 22/36] tests/qtest/bios-tables-test: Update ARM DSDT reference blobs Eric Auger
` (15 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index
Add the requested ACPI bits requested to support static acpi-index
for non hotplug ports.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/arm/virt-acpi-build.c | 12 ++++++++++++
hw/arm/Kconfig | 2 ++
2 files changed, 14 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 8768d5ce50..98d80fc88e 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -34,6 +34,7 @@
#include "hw/core/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
+#include "hw/acpi/pcihp.h"
#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
@@ -906,6 +907,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
const int *irqmap = vms->irqmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
.oem_table_id = vms->oem_table_id };
+ Aml *pci0_scope;
acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
@@ -959,6 +961,16 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
aml_append(dsdt, scope);
+ pci0_scope = aml_scope("\\_SB.PCI0");
+
+ aml_append(pci0_scope, build_pci_bridge_edsm());
+ build_append_pci_bus_devices(pci0_scope, vms->bus);
+ if (object_property_find(OBJECT(vms->bus), ACPI_PCIHP_PROP_BSEL)) {
+ build_append_pcihp_slots(pci0_scope, vms->bus);
+ }
+
+ aml_append(dsdt, pci0_scope);
+
/* copy AML table into ACPI tables blob */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 1634e26fcc..2aa4b5d778 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -34,6 +34,8 @@ config ARM_VIRT
select ACPI_HW_REDUCED
select ACPI_APEI
select ACPI_VIOT
+ select ACPI_PCIHP
+ select ACPI_PCI_BRIDGE
select VIRTIO_MEM_SUPPORTED
select ACPI_CXL
select ACPI_HMAT
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 22/36] tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (20 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 21/36] hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 23/36] hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI hotplug Eric Auger
` (14 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Changes relate to the introduction of pieces related to
acpi-index static support along with root ports with no hotplug.
+
+ Scope (\_SB.PCI0)
+ {
+ Method (EDSM, 5, Serialized)
+ {
+ If ((Arg2 == Zero))
+ {
+ Local0 = Buffer (One)
+ {
+ 0x00 // .
+ }
+ If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
+ {
+ Return (Local0)
+ }
+
+ If ((Arg1 < 0x02))
+ {
+ Return (Local0)
+ }
+
+ Local0 [Zero] = 0x81
+ Return (Local0)
+ }
+
+ If ((Arg2 == 0x07))
+ {
+ Local0 = Package (0x02)
+ {
+ Zero,
+ ""
+ }
+ Local1 = DerefOf (Arg4 [Zero])
+ Local0 [Zero] = Local1
+ Return (Local0)
+ }
+ }
+
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ }
+ }
}
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ------
tests/data/acpi/aarch64/virt/DSDT | Bin 5158 -> 5293 bytes
.../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5244 -> 5379 bytes
tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6519 -> 6654 bytes
tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7603 -> 7768 bytes
tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5360 -> 5495 bytes
tests/data/acpi/aarch64/virt/DSDT.viot | Bin 5158 -> 5310 bytes
7 files changed, 6 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 023fbc6059..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,7 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT",
-"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/DSDT.memhp",
-"tests/data/acpi/aarch64/virt/DSDT.pxb",
-"tests/data/acpi/aarch64/virt/DSDT.topology",
-"tests/data/acpi/aarch64/virt/DSDT.viot",
diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/virt/DSDT
index acab6e65febbc210158d4c39be0680bbb90250f5..18d97e8f22979411a528705c0e314acb424bbfa5 100644
GIT binary patch
delta 156
zcmZ3cu~w7ICD<iotq21H)2oeKG9vW?ZX7Xs@xe~<0nVNVBHpa7F2TOM3(O{GF%$?g
zGcqJBkeW0(Lr|DY;DY(dr@^LGz7xe?`AQyk_Fa;&fPHEv7t@l20<Ol61O|pB2@7N<
zXK}F?2(dCT@G>M6G<W1MFeDZvLL{S`xPuK0;yL0SU4j^*oA`qbEaExhIUHSrco-NM
F82~q;ELZ>l
delta 19
acmZ3hxlDu0CD<iIO@x7g>C8qh84&<B2?Wsq
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt
index 54c27e7d95b4956ed1b5dee0d299ccb08dc2a73e..2cef095bcc1bb404f8cd9ec77a879ed81c191875 100644
GIT binary patch
delta 156
zcmeyP(X7Sg66_MfEXu&Zv}_|+kx0FO8%K;@e6Uk|fU~E8h&QXNORz8R0<+0k3<ZMB
zj0_12q$W+y5ESMTxL|(rX|QRP??mxezLJNXeU~IGV4s@F#k3@$fUB`1fq`L3!UCDe
zSzPP|Laa;-ybK8i%^f)m42cDa5XtB!?qCChc#e2Smmr4dCjMXpi+GNB4o8<D9tH+R
F1_1j$EA9XQ
delta 19
acmZqH`lG?+66_LEBf`MI)VYzXNCW^oYz1ck
diff --git a/tests/data/acpi/aarch64/virt/DSDT.memhp b/tests/data/acpi/aarch64/virt/DSDT.memhp
index 4330bc97cba0950191c45ac833533db7a190db81..372ca3d7fb1e2927c7c12f97eec406d597f294ab 100644
GIT binary patch
delta 156
zcmexv^v{^fCD<k8pCkhV6Zb~0T*-O?H;x#+_+Y2_0B27F5pPykmtbGs1!j}87zzZL
z85t55NKKlYAt=lxaKZfK(_qso--+U{d?gP%`z}dXz&<sTi)l$h0as&30t3U6gatB_
zv$)s`gjksvco`B3nmckB7!nH-A(GKe+`$G0@f`7vE<p^@P5i+I7V#YM9F8tQJPZts
F3;>E4EZYD8
delta 19
acmexo{N0GlCD<jTT#|u->Fq|YTuA^&WCm0K
diff --git a/tests/data/acpi/aarch64/virt/DSDT.pxb b/tests/data/acpi/aarch64/virt/DSDT.pxb
index 7fdbc03e2bf9fb7d35704779253de36e362f0bf9..c2779882494e16920787b8ab7b4cb3c3b70f224b 100644
GIT binary patch
delta 168
zcmdmNeZz*!CD<h-LXLrf$!jCmN?BzA7p@q+_+Y2_0B27F5pPykmtbGs1!j}87zzZL
z85t55NKKl&K}IZRNx}m5shM0%OA-pW8aomg7?va~keQst#a<x9%EZ9SkWkRvk;A}{
uSda*jjBer%HZX|ih<9`eVu)^%2{y2RaCjIP7#YxH`GXCiN_iL<m>2+L6)WZd
delta 19
acmca%v)P)<CD<iovn&Gx)9sC1D`f#g-Uey_
diff --git a/tests/data/acpi/aarch64/virt/DSDT.topology b/tests/data/acpi/aarch64/virt/DSDT.topology
index 969b4f6560d3ae39f5b7e0064b7122905476fce8..ebbeedc1ed30d811315c350f4cb42f8aa265af73 100644
GIT binary patch
delta 156
zcmeyM`CW_4CD<jTT$F)<>HJ2nXCn0iZX7Xs@xe~<0nVNVBHpa7F2TOM3(O{GF%$?g
zGcqJBkeW0(Lr|DY;DY(dr@^LGz7xe?`AQyk_Fa;&fPHEv7t@l20<Ol61O|pB2@7N<
zXK}F?2(dCT@G>M6G<W1MFeDZvLL{S`xPuK0;yL0SU4j^*oA`qbEaExhIUHSrco-NM
F8359@EocA$
delta 19
acmeya^+A)%CD<k8g9rly)25AF&qM%8i3Z^S
diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch64/virt/DSDT.viot
index acab6e65febbc210158d4c39be0680bbb90250f5..b897d667971500da4732000091a6f0828d05d89e 100644
GIT binary patch
delta 173
zcmZ3cu}_oBCD<iop9lj3Q_n^&8IgJccg`5S_+Y2_0B27F5pPykmtbGs1!j}87zzZL
z85t55NKKlYAt=lxaKZfK(_qso--+U{d?gP%`z}dXz&<sTi)l$h0as&30t3U6gatB_
zv$)s`gjksvco`B3nmckB7!nH-A(GKe+`$G0@f`7vE<p^@P5i+I7V#YMl8!DxJPZts
OU=c&8G!Fv<69WJ)j4yfs
delta 19
acmdm|xlDu0CD<iIO@x7g>C8qh84&<COa$Tp
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 23/36] hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI hotplug
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (21 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 22/36] tests/qtest/bios-tables-test: Update ARM DSDT reference blobs Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 24/36] hw/acpi/ged: Add a bus link property Eric Auger
` (13 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Modify the DSDT ACPI table to enable ACPI PCI hotplug.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v4 -> v5:
- protect the access to the ged property by an acpi_dev check
v3 -> v4:
- use property accessor
- removed ACPI_PCIHP_SIZE which is already in the header
- make addition of EDSM unconditional
v2 -> v3:
- use ACPI_PCIHP_SIZE instead of 0x1000 (Igor)
- use cihp_state->use_acpi_hotplug_bridge
---
include/hw/acpi/pcihp.h | 2 ++
include/hw/arm/virt.h | 1 +
hw/acpi/pcihp.c | 1 -
hw/arm/virt-acpi-build.c | 17 +++++++++++++++++
hw/arm/virt.c | 2 ++
5 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 5506a58862..9ff548650b 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -38,6 +38,8 @@
#define ACPI_PCIHP_SEJ_BASE 0x8
#define ACPI_PCIHP_BNMR_BASE 0x10
+#define ACPI_PCIHP_SIZE 0x0018
+
typedef struct AcpiPciHpPciStatus {
uint32_t up;
uint32_t down;
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 4375819ea0..365a28b082 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -80,6 +80,7 @@ enum {
VIRT_ACPI_GED,
VIRT_NVDIMM_ACPI,
VIRT_PVTIME,
+ VIRT_ACPI_PCIHP,
VIRT_LOWMEMMAP_LAST,
};
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 2db2f16940..f1594e664a 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -43,7 +43,6 @@
#include "qobject/qnum.h"
#include "trace.h"
-#define ACPI_PCIHP_SIZE 0x0018
#define PCI_UP_BASE 0x0000
#define PCI_DOWN_BASE 0x0004
#define PCI_EJ_BASE 0x0008
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 98d80fc88e..f8767a341c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -969,6 +969,23 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_pcihp_slots(pci0_scope, vms->bus);
}
+ if (vms->acpi_dev) {
+ bool acpi_pcihp;
+
+ acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
+ ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
+ NULL);
+
+ if (acpi_pcihp) {
+ build_acpi_pci_hotplug(dsdt, AML_SYSTEM_MEMORY,
+ memmap[VIRT_ACPI_PCIHP].base);
+ build_append_pcihp_resources(pci0_scope,
+ memmap[VIRT_ACPI_PCIHP].base,
+ memmap[VIRT_ACPI_PCIHP].size);
+
+ build_append_notification_callback(pci0_scope, vms->bus);
+ }
+ }
aml_append(dsdt, pci0_scope);
/* copy AML table into ACPI tables blob */
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8070ff7b11..817adedb31 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -76,6 +76,7 @@
#include "standard-headers/linux/input.h"
#include "hw/arm/smmuv3.h"
#include "hw/acpi/acpi.h"
+#include "hw/acpi/pcihp.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
@@ -186,6 +187,7 @@ static const MemMapEntry base_memmap[] = {
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
[VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
[VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
+ [VIRT_ACPI_PCIHP] = { 0x090c0000, ACPI_PCIHP_SIZE },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 24/36] hw/acpi/ged: Add a bus link property
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (22 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 23/36] hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI hotplug Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 25/36] hw/arm/virt: Pass the bus on the ged creation Eric Auger
` (12 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
This property will be set by the machine code on the object
creation. It will be used by acpi pcihp hotplug code.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
hw/acpi/generic_event_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index 7831db412b..ef1c1ec51f 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -13,6 +13,7 @@
#include "qapi/error.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/generic_event_device.h"
+#include "hw/pci/pci.h"
#include "hw/irq.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
@@ -320,6 +321,8 @@ static const Property acpi_ged_properties[] = {
DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0),
DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, AcpiGedState,
pcihp_state.use_acpi_hotplug_bridge, 0),
+ DEFINE_PROP_LINK("bus", AcpiGedState, pcihp_state.root,
+ TYPE_PCI_BUS, PCIBus *),
};
static const VMStateDescription vmstate_memhp_state = {
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 25/36] hw/arm/virt: Pass the bus on the ged creation
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (23 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 24/36] hw/acpi/ged: Add a bus link property Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 26/36] hw/acpi/ged: Call pcihp plug callbacks in hotplug handler implementation Eric Auger
` (11 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
The bus will be needed on ged realize for acpi pci hp setup.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 817adedb31..41b5086b55 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -701,6 +701,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
+ object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 26/36] hw/acpi/ged: Call pcihp plug callbacks in hotplug handler implementation
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (24 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 25/36] hw/arm/virt: Pass the bus on the ged creation Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 27/36] hw/acpi/pcihp: Remove root arg in acpi_pcihp_init Eric Auger
` (10 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Add PCI device related code in the TYPE_HOTPLUG_HANDLER
implementation.
For a PCI device hotplug/hotunplug event, the code routes to
acpi_pcihp_device callbacks (pre_plug_cb, plug_cb, unplug_request_cb,
unplug_cb).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
v2 -> v4:
moved before "hw/acpi/ged: Prepare the device to react to PCI hotplug
events" (Igor)
v2 -> v3:
- remove else block in acpi_ged_device_pre_plug_cb
---
hw/acpi/generic_event_device.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index ef1c1ec51f..92b931758f 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -17,6 +17,7 @@
#include "hw/irq.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
+#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
@@ -228,6 +229,14 @@ static const MemoryRegionOps ged_regs_ops = {
},
};
+static void acpi_ged_device_pre_plug_cb(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error **errp)
+{
+ if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
+ acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
+ }
+}
+
static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
@@ -241,6 +250,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
}
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
+ acpi_pcihp_device_plug_cb(hotplug_dev, &s->pcihp_state, dev, errp);
} else {
error_setg(errp, "virt: device plug request for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -257,6 +268,9 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
+ acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->pcihp_state,
+ dev, errp);
} else {
error_setg(errp, "acpi: device unplug request for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -272,6 +286,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
+ acpi_pcihp_device_unplug_cb(hotplug_dev, &s->pcihp_state, dev, errp);
} else {
error_setg(errp, "acpi: device unplug for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -485,6 +501,7 @@ static void acpi_ged_class_init(ObjectClass *class, const void *data)
dc->vmsd = &vmstate_acpi_ged;
dc->realize = acpi_ged_realize;
+ hc->pre_plug = acpi_ged_device_pre_plug_cb;
hc->plug = acpi_ged_device_plug_cb;
hc->unplug_request = acpi_ged_unplug_request_cb;
hc->unplug = acpi_ged_unplug_cb;
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 27/36] hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (25 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 26/36] hw/acpi/ged: Call pcihp plug callbacks in hotplug handler implementation Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 28/36] hw/acpi/ged: Prepare the device to react to PCI hotplug events Eric Auger
` (9 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Let pass the root bus to ich9 and piix4 through a property link
instead of through an argument passed to acpi_pcihp_init().
Also make sure the root bus is set at the entry of acpi_pcihp_init().
The rationale of that change is to be consistent with the forecoming ARM
implementation where the machine passes the root bus (steming from GPEX)
to the GED device through a link property.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/acpi/pcihp.h | 2 +-
hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
hw/acpi/ich9.c | 7 ++++++-
hw/acpi/pcihp.c | 4 ++--
hw/acpi/piix4.c | 5 ++++-
5 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 9ff548650b..ca6a258825 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -62,7 +62,7 @@ typedef struct AcpiPciHpState {
bool use_acpi_root_pci_hotplug;
} AcpiPciHpState;
-void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
+void acpi_pcihp_init(Object *owner, AcpiPciHpState *,
MemoryRegion *io, uint16_t io_base);
bool acpi_pcihp_is_hotpluggable_bus(AcpiPciHpState *s, BusState *bus);
diff --git a/hw/acpi/acpi-pci-hotplug-stub.c b/hw/acpi/acpi-pci-hotplug-stub.c
index b7bc6e40a1..d58ea726a8 100644
--- a/hw/acpi/acpi-pci-hotplug-stub.c
+++ b/hw/acpi/acpi-pci-hotplug-stub.c
@@ -4,7 +4,7 @@
const VMStateDescription vmstate_acpi_pcihp_pci_status;
-void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
+void acpi_pcihp_init(Object *owner, AcpiPciHpState *s,
MemoryRegion *address_space_io, uint16_t io_base)
{
}
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 967b67485e..2b3b493c01 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -322,9 +322,10 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
}
if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) {
+ object_property_set_link(OBJECT(lpc_pci), "bus",
+ OBJECT(pci_get_bus(lpc_pci)), &error_abort);
acpi_pcihp_init(OBJECT(lpc_pci),
&pm->acpi_pci_hotplug,
- pci_get_bus(lpc_pci),
pci_address_space_io(lpc_pci),
ACPI_PCIHP_ADDR_ICH9);
@@ -428,6 +429,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
&pm->pm_io_base, OBJ_PROP_FLAG_READ);
+ object_property_add_link(obj, "bus", TYPE_PCI_BUS,
+ (Object **)&pm->acpi_pci_hotplug.root,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_STRONG);
object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
ich9_pm_get_gpe0_blk,
NULL, NULL, pm);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index f1594e664a..4922bbc778 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -493,13 +493,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
},
};
-void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
+void acpi_pcihp_init(Object *owner, AcpiPciHpState *s,
MemoryRegion *io, uint16_t io_base)
{
s->io_len = ACPI_PCIHP_SIZE;
s->io_base = io_base;
- s->root = root_bus;
+ assert(s->root);
memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
"acpi-pci-hotplug", s->io_len);
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index d98b80df6d..7a18f18dda 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -567,7 +567,8 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge ||
s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) {
- acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
+ object_property_set_link(OBJECT(s), "bus", OBJECT(bus), &error_abort);
+ acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, parent,
ACPI_PCIHP_ADDR_PIIX4);
qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s));
}
@@ -611,6 +612,8 @@ static const Property piix4_pm_properties[] = {
acpi_pci_hotplug.use_acpi_hotplug_bridge, true),
DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState,
acpi_pci_hotplug.use_acpi_root_pci_hotplug, true),
+ DEFINE_PROP_LINK("bus", PIIX4PMState, acpi_pci_hotplug.root,
+ TYPE_PCI_BUS, PCIBus *),
DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
acpi_memory_hotplug.is_enabled, true),
DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 28/36] hw/acpi/ged: Prepare the device to react to PCI hotplug events
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (26 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 27/36] hw/acpi/pcihp: Remove root arg in acpi_pcihp_init Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 29/36] hw/acpi/ged: Support migration of AcpiPciHpState Eric Auger
` (8 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
QEMU will notify the OS about PCI hotplug/hotunplug events through
GED interrupts. Let the GED device handle a new PCI hotplug event.
On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK
mutex held.
The GED device uses a dedicated MMIO region that will be mapped
by the machine code.
At this point the GED still does not support PCI device hotplug in
its TYPE_HOTPLUG_HANDLER implementation. This will come in a
subsequent patch.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v4 -> v5:
- Get rid of legacy reset API
v3 -> v4:
- add qbus_set_hotplug_handler
- root bus is not passed in acpi_pcihp_init arg
v2 -> v3:
- pcihp_init and reset are put in ged code instead of machine code
(Igor)
- Add ACPI_GED_PCI_HOTPLUG_EVT event depending on use_acpi_hotplug_bridge
(Igor)
v1 -> v2:
- Introduce ACPI_PCIHP_REGION_NAME
---
include/hw/acpi/generic_event_device.h | 14 ++++++++++-
hw/acpi/generic_event_device.c | 35 ++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
index f5ffa67a39..d56adaa626 100644
--- a/include/hw/acpi/generic_event_device.h
+++ b/include/hw/acpi/generic_event_device.h
@@ -69,7 +69,7 @@
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
#define TYPE_ACPI_GED "acpi-ged"
-OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
+OBJECT_DECLARE_TYPE(AcpiGedState, AcpiGedClass, ACPI_GED)
#define ACPI_GED_EVT_SEL_OFFSET 0x0
#define ACPI_GED_EVT_SEL_LEN 0x4
@@ -102,6 +102,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
#define ACPI_GED_PWR_DOWN_EVT 0x2
#define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
+#define ACPI_GED_PCI_HOTPLUG_EVT 0x10
typedef struct GEDState {
MemoryRegion evt;
@@ -109,6 +110,8 @@ typedef struct GEDState {
uint32_t sel;
} GEDState;
+#define ACPI_PCIHP_REGION_NAME "pcihp container"
+
struct AcpiGedState {
SysBusDevice parent_obj;
MemHotplugState memhp_state;
@@ -116,12 +119,21 @@ struct AcpiGedState {
CPUHotplugState cpuhp_state;
MemoryRegion container_cpuhp;
AcpiPciHpState pcihp_state;
+ MemoryRegion container_pcihp;
GEDState ged_state;
uint32_t ged_event_bitmap;
qemu_irq irq;
AcpiGhesState ghes_state;
};
+typedef struct AcpiGedClass {
+ /* <private> */
+ SysBusDeviceClass parent_class;
+
+ /*< public >*/
+ ResettablePhases parent_phases;
+} AcpiGedClass;
+
void build_ged_aml(Aml *table, const char* name, HotplugHandler *hotplug_dev,
uint32_t ged_irq, AmlRegionSpace rs, hwaddr ged_base);
void acpi_dsdt_add_power_button(Aml *scope);
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index 92b931758f..7535d07737 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/acpi/acpi.h"
+#include "hw/acpi/pcihp.h"
#include "hw/acpi/generic_event_device.h"
#include "hw/pci/pci.h"
#include "hw/irq.h"
@@ -28,6 +29,7 @@ static const uint32_t ged_supported_events[] = {
ACPI_GED_PWR_DOWN_EVT,
ACPI_GED_NVDIMM_HOTPLUG_EVT,
ACPI_GED_CPU_HOTPLUG_EVT,
+ ACPI_GED_PCI_HOTPLUG_EVT,
};
/*
@@ -123,6 +125,12 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev,
aml_notify(aml_name("\\_SB.NVDR"),
aml_int(0x80)));
break;
+ case ACPI_GED_PCI_HOTPLUG_EVT:
+ aml_append(if_ctx,
+ aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
+ aml_append(if_ctx, aml_call0("\\_SB.PCI0.PCNT"));
+ aml_append(if_ctx, aml_release(aml_name("\\_SB.PCI0.BLCK")));
+ break;
default:
/*
* Please make sure all the events in ged_supported_events[]
@@ -316,6 +324,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
} else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
sel = ACPI_GED_CPU_HOTPLUG_EVT;
+ } else if (ev & ACPI_PCI_HOTPLUG_STATUS) {
+ sel = ACPI_GED_PCI_HOTPLUG_EVT;
} else {
/* Unknown event. Return without generating interrupt. */
warn_report("GED: Unsupported event %d. No irq injected", ev);
@@ -427,9 +437,13 @@ static void acpi_ged_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AcpiGedState *s = ACPI_GED(dev);
+ AcpiPciHpState *pcihp_state = &s->pcihp_state;
uint32_t ged_events;
int i;
+ if (pcihp_state->use_acpi_hotplug_bridge) {
+ s->ged_event_bitmap |= ACPI_GED_PCI_HOTPLUG_EVT;
+ }
ged_events = ctpop32(s->ged_event_bitmap);
for (i = 0; i < ARRAY_SIZE(ged_supported_events) && ged_events; i++) {
@@ -449,6 +463,13 @@ static void acpi_ged_realize(DeviceState *dev, Error **errp)
cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
&s->cpuhp_state, 0);
break;
+ case ACPI_GED_PCI_HOTPLUG_EVT:
+ memory_region_init(&s->container_pcihp, OBJECT(dev),
+ ACPI_PCIHP_REGION_NAME, ACPI_PCIHP_SIZE);
+ sysbus_init_mmio(sbd, &s->container_pcihp);
+ acpi_pcihp_init(OBJECT(s), &s->pcihp_state,
+ &s->container_pcihp, 0);
+ qbus_set_hotplug_handler(BUS(s->pcihp_state.root), OBJECT(dev));
}
ged_events--;
}
@@ -490,11 +511,22 @@ static void acpi_ged_initfn(Object *obj)
sysbus_init_mmio(sbd, &ged_st->regs);
}
+static void ged_reset_hold(Object *obj, ResetType type)
+{
+ AcpiGedState *s = ACPI_GED(obj);
+
+ if (s->pcihp_state.use_acpi_hotplug_bridge) {
+ acpi_pcihp_reset(&s->pcihp_state);
+ }
+}
+
static void acpi_ged_class_init(ObjectClass *class, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(class);
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(class);
+ ResettableClass *rc = RESETTABLE_CLASS(class);
+ AcpiGedClass *gedc = ACPI_GED_CLASS(class);
dc->desc = "ACPI Generic Event Device";
device_class_set_props(dc, acpi_ged_properties);
@@ -505,6 +537,8 @@ static void acpi_ged_class_init(ObjectClass *class, const void *data)
hc->plug = acpi_ged_device_plug_cb;
hc->unplug_request = acpi_ged_unplug_request_cb;
hc->unplug = acpi_ged_unplug_cb;
+ resettable_class_set_parent_phases(rc, NULL, ged_reset_hold, NULL,
+ &gedc->parent_phases);
adevc->ospm_status = acpi_ged_ospm_status;
adevc->send_event = acpi_ged_send_event;
@@ -516,6 +550,7 @@ static const TypeInfo acpi_ged_info = {
.instance_size = sizeof(AcpiGedState),
.instance_init = acpi_ged_initfn,
.class_init = acpi_ged_class_init,
+ .class_size = sizeof(AcpiGedClass),
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ TYPE_ACPI_DEVICE_IF },
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 29/36] hw/acpi/ged: Support migration of AcpiPciHpState
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (27 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 28/36] hw/acpi/ged: Prepare the device to react to PCI hotplug events Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 30/36] hw/core/sysbus: Introduce sysbus_mmio_map_name() helper Eric Auger
` (7 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Add a subsection to migrate the AcpiPciHpState state.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Prasad Pandit <pjp@fedoraproject.org>
---
hw/acpi/generic_event_device.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index 7535d07737..95682b79a2 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -417,6 +417,25 @@ static const VMStateDescription vmstate_ghes_state = {
}
};
+static bool pcihp_needed(void *opaque)
+{
+ AcpiGedState *s = opaque;
+ return s->pcihp_state.use_acpi_hotplug_bridge;
+}
+
+static const VMStateDescription vmstate_pcihp_state = {
+ .name = "acpi-ged/pcihp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pcihp_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_PCI_HOTPLUG(pcihp_state,
+ AcpiGedState,
+ NULL, NULL),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_acpi_ged = {
.name = "acpi-ged",
.version_id = 1,
@@ -429,6 +448,7 @@ static const VMStateDescription vmstate_acpi_ged = {
&vmstate_memhp_state,
&vmstate_cpuhp_state,
&vmstate_ghes_state,
+ &vmstate_pcihp_state,
NULL
}
};
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 30/36] hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (28 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 29/36] hw/acpi/ged: Support migration of AcpiPciHpState Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 31/36] hw/arm/virt: Minor code reshuffling in create_acpi_ged Eric Auger
` (6 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Some sysbus devices have conditional mmio regions. This
happens for instance with the hw/acpi/ged device. In that case
it becomes difficult to predict which index a specific MMIO
region corresponds to when one needs to mmio map the region.
Introduce a new helper that takes the name of the region instead
of its index. If the region is not found this returns -1.
Otherwise it maps the corresponding index and returns this latter.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/sysbus.h | 1 +
hw/core/sysbus.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
index 7dc88aaa27..18fde8a7b4 100644
--- a/include/hw/sysbus.h
+++ b/include/hw/sysbus.h
@@ -82,6 +82,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
bool sysbus_is_irq_connected(SysBusDevice *dev, int n);
qemu_irq sysbus_get_connected_irq(SysBusDevice *dev, int n);
void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
+int sysbus_mmio_map_name(SysBusDevice *dev, const char*name, hwaddr addr);
void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
int priority);
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index e71367adfb..ec69e877a2 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -151,6 +151,17 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
sysbus_mmio_map_common(dev, n, addr, false, 0);
}
+int sysbus_mmio_map_name(SysBusDevice *dev, const char *name, hwaddr addr)
+{
+ for (int i = 0; i < dev->num_mmio; i++) {
+ if (!strcmp(dev->mmio[i].memory->name, name)) {
+ sysbus_mmio_map(dev, i, addr);
+ return i;
+ }
+ }
+ return -1;
+}
+
void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
int priority)
{
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 31/36] hw/arm/virt: Minor code reshuffling in create_acpi_ged
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (29 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 30/36] hw/core/sysbus: Introduce sysbus_mmio_map_name() helper Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 32/36] hw/arm/virt: Let virt support pci hotplug/unplug GED event Eric Auger
` (5 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Use a local SysBusDevice handle. Also use the newly introduced
sysbus_mmio_map_name which brings better readability about the region
being mapped. GED device has regions which exist depending on some
external properties and it becomes difficult to guess the index of
a region. Better refer to a region by its name.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/acpi/generic_event_device.h | 1 +
hw/arm/virt.c | 11 +++++++----
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
index d56adaa626..2c5b055327 100644
--- a/include/hw/acpi/generic_event_device.h
+++ b/include/hw/acpi/generic_event_device.h
@@ -111,6 +111,7 @@ typedef struct GEDState {
} GEDState;
#define ACPI_PCIHP_REGION_NAME "pcihp container"
+#define ACPI_MEMHP_REGION_NAME "memhp container"
struct AcpiGedState {
SysBusDevice parent_obj;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 41b5086b55..f127a668ef 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -688,6 +688,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
{
DeviceState *dev;
MachineState *ms = MACHINE(vms);
+ SysBusDevice *sbdev;
int irq = vms->irqmap[VIRT_ACPI_GED];
uint32_t event = ACPI_GED_PWR_DOWN_EVT;
@@ -702,11 +703,13 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sbdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbdev, &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
+ sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].base);
+ sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME,
+ vms->memmap[VIRT_PCDIMM_ACPI].base);
+ sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq));
return dev;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 32/36] hw/arm/virt: Let virt support pci hotplug/unplug GED event
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (30 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 31/36] hw/arm/virt: Minor code reshuffling in create_acpi_ged Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 33/36] tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp tests Eric Auger
` (4 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
Set up the IO registers used to communicate between QEMU
and ACPI.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v2 -> v3:
- remove acpi_ged_state->pcihp_state.use_acpi_hotplug_bridge = true;
- use sysbus_mmio_map_name for all regs (Igor)
- create_pcie left at its original place
v1 -> v2:
- use ACPI_PCIHP_REGION_NAME
---
hw/arm/virt.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f127a668ef..ef6be3660f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -691,6 +691,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
SysBusDevice *sbdev;
int irq = vms->irqmap[VIRT_ACPI_GED];
uint32_t event = ACPI_GED_PWR_DOWN_EVT;
+ bool acpi_pcihp;
if (ms->ram_slots) {
event |= ACPI_GED_MEM_HOTPLUG_EVT;
@@ -709,6 +710,18 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME,
vms->memmap[VIRT_PCDIMM_ACPI].base);
+
+ acpi_pcihp = object_property_get_bool(OBJECT(dev),
+ ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, NULL);
+
+ if (acpi_pcihp) {
+ int pcihp_region_index;
+
+ pcihp_region_index = sysbus_mmio_map_name(sbdev, ACPI_PCIHP_REGION_NAME,
+ vms->memmap[VIRT_ACPI_PCIHP].base);
+ assert(pcihp_region_index >= 0);
+ }
+
sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq));
return dev;
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 33/36] tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp tests
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (31 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 32/36] hw/arm/virt: Let virt support pci hotplug/unplug GED event Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 34/36] tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test Eric Auger
` (3 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
From: Gustavo Romero <gustavo.romero@linaro.org>
Soon we will introduce new tests related to ACPI PCI hotplug and
acpi-index that will use a new reference blob:
tests/data/acpi/aarch64/virt/DSDT.acpipcihp
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v3 -> v4:
- switch Sign-off's (Jonathan)
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | 0
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | 0
3 files changed, 2 insertions(+)
create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..02f4f0b29f 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
+"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpipcihp b/tests/data/acpi/aarch64/virt/DSDT.acpipcihp
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex b/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
new file mode 100644
index 0000000000..e69de29bb2
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 34/36] tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (32 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 33/36] tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp tests Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 35/36] qtest/bios-tables-test: Generate reference blob for DSDT.hpoffacpiindex Eric Auger
` (2 subsequent siblings)
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
From: Gustavo Romero <gustavo.romero@linaro.org>
Add 2 new tests:
- test_acpi_aarch64_virt_acpi_pci_hotplug tests the acpi pci hotplug
using -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
- test_acpi_aarch64_virt_pcie_root_port_hpoff tests static-acpi index
on a root port with disabled hotplug
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v3 -> v4:
- add -device pci-testdev for the first test case
- fix the chassis
- add a test for static acpi-index
---
tests/qtest/bios-tables-test.c | 52 ++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 357bcefd37..1074b8d67a 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1643,6 +1643,54 @@ static void test_acpi_aarch64_virt_tcg_memhp(void)
}
+static void test_acpi_aarch64_virt_acpi_pci_hotplug(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "aarch64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 256ULL * MiB,
+ .variant = ".acpipcihp",
+ };
+
+ /* Use ACPI PCI Hotplug */
+ test_acpi_one(" -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on"
+ " -cpu cortex-a57"
+ " -device pcie-root-port,id=pcie.1,bus=pcie.0,chassis=0,slot=1,addr=7.0"
+ " -device pci-testdev,bus=pcie.1",
+ &data);
+
+ free_test_data(&data);
+}
+
+static void test_acpi_aarch64_virt_pcie_root_port_hpoff(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "aarch64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 256ULL * MiB,
+ .variant = ".hpoffacpiindex",
+ };
+
+ /* turn hotplug off on the pcie-root-port and use static acpi-index*/
+ test_acpi_one(" -device pcie-root-port,id=pcie.1,chassis=0,"
+ "slot=1,hotplug=off,addr=7.0"
+ " -device pci-testdev,bus=pcie.1,acpi-index=12"
+ " -cpu cortex-a57",
+ &data);
+
+ free_test_data(&data);
+}
+
static void test_acpi_microvm_prepare(test_data *data)
{
data->machine = "microvm";
@@ -2602,6 +2650,10 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt/numamem",
test_acpi_aarch64_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_aarch64_virt_tcg_memhp);
+ qtest_add_func("acpi/virt/acpipcihp",
+ test_acpi_aarch64_virt_acpi_pci_hotplug);
+ qtest_add_func("acpi/virt/hpoffacpiindex",
+ test_acpi_aarch64_virt_pcie_root_port_hpoff);
qtest_add_func("acpi/virt/pxb", test_acpi_aarch64_virt_tcg_pxb);
qtest_add_func("acpi/virt/oem-fields",
test_acpi_aarch64_virt_oem_fields);
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 35/36] qtest/bios-tables-test: Generate reference blob for DSDT.hpoffacpiindex
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (33 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 34/36] tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 8:05 ` [PATCH v7 36/36] qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp Eric Auger
2025-07-14 19:40 ` [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Jonathan Cameron via
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
The disassembled DSDT table is given below
* Original Table Header:
* Signature "DSDT"
* Length 0x000014E3 (5347)
* Revision 0x02
* Checksum 0x92
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
Device (COM0)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09000000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000021,
}
})
}
Device (FWCF)
{
Name (_HID, "QEMU0002") // _HID: Hardware ID
Name (_STA, 0x0B) // _STA: Status
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09020000, // Address Base
0x00000018, // Address Length
)
})
}
Device (VR00)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000030,
}
})
}
../..
Device (L000)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
../..
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, Zero) // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
{
Package (0x04)
{
0xFFFF,
Zero,
L000,
Zero
},
../..
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
Return (0x0000004010000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum
0x3EFF0000, // Translation Offset
0x00010000, // Length
,, , TypeStatic, DenseTranslation)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000008000000000, // Range Minimum
0x000000FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000008000000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
CDW3 = Local0
}
Else
{
CDW1 |= 0x04
}
Return (Arg3)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x01 // .
})
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000004010000000, // Range Minimum
0x000000401FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
}
})
OperationRegion (EREG, SystemMemory, 0x09080000, 0x04)
Field (EREG, DWordAcc, NoLock, WriteAsZeros)
{
ESEL, 32
}
Method (_EVT, 1, Serialized) // _EVT: Event
{
Local0 = ESEL /* \_SB_.GED_.ESEL */
If (((Local0 & 0x02) == 0x02))
{
Notify (PWRB, 0x80) // Status Change
}
}
}
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
}
Scope (\_SB.PCI0)
{
Method (EDSM, 5, Serialized)
{
If ((Arg2 == Zero))
{
Local0 = Buffer (One)
{
0x00 // .
}
If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Return (Local0)
}
If ((Arg1 < 0x02))
{
Return (Local0)
}
Local0 [Zero] = 0x81
Return (Local0)
}
If ((Arg2 == 0x07))
{
Local0 = Package (0x02)
{
Zero,
""
}
Local1 = DerefOf (Arg4 [Zero])
Local0 [Zero] = Local1
Return (Local0)
}
}
Device (S00)
{
Name (_ADR, Zero) // _ADR: Address
}
Device (S08)
{
Name (_ADR, 0x00010000) // _ADR: Address
}
Device (S38)
{
Name (_ADR, 0x00070000) // _ADR: Address
Device (S00)
{
Name (_ADR, Zero) // _ADR: Address
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x01)
{
0x0C
}
Return (EDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
}
}
}
}
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v5 -> v6:
cropped the commit description
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 02f4f0b29f..dc3ab24d05 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1,2 @@
/* List of comma-separated changed AML files to ignore */
"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
-"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
diff --git a/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex b/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..970d43f68bca060361105f70dbb00b3a25646db4 100644
GIT binary patch
literal 5347
zcmZvgOK%!i6oAjb0K+ig;bCKAY)F$veMSTLl{8HQGuS2pn=(#ZiAY0KrHbt?kQ!A=
zqe>2yk~F*8YS&cq52@5ucinZ-Wz|jpKzF6Oa|inz<;()+KF)XVH=L0U*KwV_zj6Sf
zlg6&S?Uoy#b?tJwTvh-;+>3AX`EBKa=Qh0ls9;-`rFq*eCt0_<Ez7djLG$jl9O#d3
z*t?zSSg*5fS(QpKrg?VHO&9e1i#P~i987@kqo6340N^R~M;n{__NL^1+U(r3EUOBd
z=kC?@gyz|HU6F{io|1@Ad_IV*tM_};Ewy)gyOw3GUMzbad9k<-p<r<fBPw!riV(}b
zfe0Z)B|tR9E~*?t4{;0?F{+qRV;NzN5k-s|W~{Ibm1Ag#v4R<^EF;1(bi`Q2j5U@K
z<roHHtYOAF%ZPD|6k@Dn#s<sKIEINB8<=sOWyCo~1~IN9MkRPTXo~4N$H*bZ4a{KE
zl)fa>RG&kPk1&JJQ-j;bJYw9$3_eej9HW33A7cierzwt6M2uUQ!RP4=$5=*;PcVbe
zQ<Gzq5#u&y@Ohf%7;hm)9W(em&2Wq>h|$0dK2Nh8<0@j<h*9P9G{-UCK@0~o_&lBE
z81ErQ6EpZco#PlEAjT$U@Ohf&7}pSE3p4mUo#z-9Vr*jupQj5Pqly?U%;591z%f=3
z;|^x<dAi6k))3<^X7G7h<QN->(Z&ouPnS5x4aDdmMvc$YWsY$ZF?KM6&(jjexP=(I
z0i&h1&kLgNPS>)n&GX`;+jG+?J>l0mm;L#&h@pMCsOR=vr7uyzb_hz*2<i%hl6~i>
zJ7QPC+e1*I7{S|mn_<a5$_m~h$_i7~RfZ+|E?6gByA}Luf>pOR#4~9*L8~TezUCHa
zUZb&d{v6%CUb>_gyI?~L9zhu_D1!r!;A=R5&*2e(fcRxvx3`yVf2AL15^7>H0rA^_
zyjR+mRe_8l`t^`_Jkv(FZCN$QBvoTFQ9#60&RZg?3YnA~^W$n4O%Z7Yb3=Y)^}Hn_
zr&B{R(h4F&;73kZ3Hy=L9fbYJ>C~`{tOSu^897}=^&_V{Q2og1R8>Y!H?PXb=_(Q8
z86ln#>KT!d(^aCxGfF(8)H6ywW5hE?JY&=|Mm;s+sS!_&dTP`&PCVnpGfq9@)Ke#(
zI`P!0r%pW+#4|xW6Vx+7Jq_Y%5Kn`88q_mMJd?yTNj;O)Geta8#4|-bQ`B>Yc+L>d
z8R|JhJx$_i5>JzQn$$B*Jk!K8O+C}pGebNx#4|%ZGt@InJhQ|zOFgsHGe<mg#4|@d
zbJTN|c+L{fS?W1UJ?Dt$9Pyl^o^#YQPdxL)GfzG9)N`JA&J)jh>N!t67l`Kq@m!#u
z3)HhfJPX9LKs^i8bCGy163<2Ixkx>W#Ir~|i`277J(q~*67gK3o=enonRqS}&t>Yl
zOg&4)vqU^g)U!18%$c6usKZ%Gocf6WH?m^cj_FTcB_U*hxF+I5d6@?=#9@xO%*o_G
z@wZHjUVE7b#R$t5z{H<ExdouW>-SNNe;xZXCUO$GME_IBwPW6{Ypbu1z;^a4<DJOq
z<8)Rx`<*{)|CWlkf7*Xi|K;O9zIc74tG2UWeSM^BwzFRwijTpwfnFMn&6Cpu<y#T%
zk5$ImlT&|K_L*X2I1oKQ8?sBFDrZNz4?V~2sN+j=&EMC5``caprt?GopU%Rsc4r(v
zJ%qD#SW(0W^hX`F*K|>FWBW%~;^3>MTW^^APj@nzl*Cg;mnrVWiC81{;F>sd+iE(V
zJbRD_ZWU1^-D^3?t)@c?%CPdT3_Wi4np<E1XmMTbKTn9J-E^Dna&F0M-rtK4MPo2F
zPoE8RQJcKz?)Mt{aeuTRZscOJ)U$&k%xov*Zbbc-yBldbZYMcjJ3WM<kROZ-C;U@7
z8;oN=9_XR7!BBtxY5;IH7#B|u_1G{I2|*GD!|z^w3Gi_EP!9G-3D>eb&8s^-=#OSx
qYeO~+kw5*>id(zrh(UjJ`C@u5FMcp%m{Aqo7@UbcK0Y`+8vG9j4In)L
literal 0
HcmV?d00001
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v7 36/36] qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (34 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 35/36] qtest/bios-tables-test: Generate reference blob for DSDT.hpoffacpiindex Eric Auger
@ 2025-07-14 8:05 ` Eric Auger
2025-07-14 19:40 ` [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Jonathan Cameron via
36 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 8:05 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, peter.maydell,
imammedo, Jonathan.Cameron, gustavo.romero, anisinha, mst,
shannon.zhaosl
Cc: pbonzini, philmd, alex.bennee
The disassembled DSDT table is given below.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20210604 (64-bit version)
* Copyright (c) 2000 - 2021 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of ../tests/data/acpi/aarch64/virt/DSDT.acpipcihp, Thu Jul 3 05:16:27 2025
*
* Original Table Header:
* Signature "DSDT"
* Length 0x0000183A (6202)
* Revision 0x02
* Checksum 0x98
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
Device (COM0)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09000000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000021,
}
})
}
Device (FWCF)
{
Name (_HID, "QEMU0002") // _HID: Hardware ID
Name (_STA, 0x0B) // _STA: Status
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09020000, // Address Base
0x00000018, // Address Length
)
})
}
Device (VR00)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000030,
}
})
}
../..
Device (L000)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
../..
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, Zero) // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
{
Package (0x04)
{
0xFFFF,
Zero,
L000,
Zero
},
../..
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
Return (0x0000004010000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum
0x3EFF0000, // Translation Offset
0x00010000, // Length
,, , TypeStatic, DenseTranslation)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000008000000000, // Range Minimum
0x000000FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000008000000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
Local0 &= 0x1E
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
CDW3 = Local0
}
Else
{
CDW1 |= 0x04
}
Return (Arg3)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x01 // .
})
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000004010000000, // Range Minimum
0x000000401FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
}
})
OperationRegion (EREG, SystemMemory, 0x09080000, 0x04)
Field (EREG, DWordAcc, NoLock, WriteAsZeros)
{
ESEL, 32
}
Method (_EVT, 1, Serialized) // _EVT: Event
{
Local0 = ESEL /* \_SB_.GED_.ESEL */
If (((Local0 & 0x02) == 0x02))
{
Notify (PWRB, 0x80) // Status Change
}
If (((Local0 & 0x10) == 0x10))
{
Acquire (\_SB.PCI0.BLCK, 0xFFFF)
\_SB.PCI0.PCNT ()
Release (\_SB.PCI0.BLCK)
}
}
}
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
}
Scope (_SB.PCI0)
{
OperationRegion (PCST, SystemMemory, 0x090C0000, 0x08)
Field (PCST, DWordAcc, NoLock, WriteAsZeros)
{
PCIU, 32,
PCID, 32
}
OperationRegion (SEJ, SystemMemory, 0x090C0008, 0x04)
Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
{
B0EJ, 32
}
OperationRegion (BNMR, SystemMemory, 0x090C0010, 0x08)
Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
{
BNUM, 32,
PIDX, 32
}
Mutex (BLCK, 0x00)
Method (PCEJ, 2, NotSerialized)
{
Acquire (BLCK, 0xFFFF)
BNUM = Arg0
B0EJ = (One << Arg1)
Release (BLCK)
Return (Zero)
}
Method (AIDX, 2, NotSerialized)
{
Acquire (BLCK, 0xFFFF)
BNUM = Arg0
PIDX = (One << Arg1)
Local0 = PIDX /* \_SB_.PCI0.PIDX */
Release (BLCK)
Return (Local0)
}
Method (PDSM, 5, Serialized)
{
If ((Arg2 == Zero))
{
Local0 = Buffer (One)
{
0x00 // .
}
If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Return (Local0)
}
If ((Arg1 < 0x02))
{
Return (Local0)
}
Local1 = Zero
Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
))
If (!((Local2 == Zero) | (Local2 == 0xFFFFFFFF)))
{
Local1 |= One
Local1 |= (One << 0x07)
}
Local0 [Zero] = Local1
Return (Local0)
}
If ((Arg2 == 0x07))
{
Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
))
Local0 = Package (0x02) {}
If (!((Local2 == Zero) || (Local2 == 0xFFFFFFFF)))
{
Local0 [Zero] = Local2
Local0 [One] = ""
}
Return (Local0)
}
}
}
Scope (\_SB.PCI0)
{
Method (EDSM, 5, Serialized)
{
If ((Arg2 == Zero))
{
Local0 = Buffer (One)
{
0x00 // .
}
If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Return (Local0)
}
If ((Arg1 < 0x02))
{
Return (Local0)
}
Local0 [Zero] = 0x81
Return (Local0)
}
If ((Arg2 == 0x07))
{
Local0 = Package (0x02)
{
Zero,
""
}
Local1 = DerefOf (Arg4 [Zero])
Local0 [Zero] = Local1
Return (Local0)
}
}
Device (S00)
{
Name (_ADR, Zero) // _ADR: Address
}
Device (S08)
{
Name (_ADR, 0x00010000) // _ADR: Address
}
Device (S38)
{
Name (_ADR, 0x00070000) // _ADR: Address
Device (S00)
{
Name (_ADR, Zero) // _ADR: Address
}
Name (BSEL, One)
Scope (S00)
{
Name (ASUN, Zero)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
Zero,
Zero
}
Local0 [Zero] = BSEL /* \_SB_.PCI0.S38_.BSEL */
Local0 [One] = ASUN /* \_SB_.PCI0.S38_.S00_.ASUN */
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
Name (_SUN, Zero) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
PCEJ (BSEL, _SUN)
}
}
Method (DVNT, 2, NotSerialized)
{
If ((Arg0 & One))
{
Notify (S00, Arg1)
}
}
}
Name (BSEL, Zero)
Scope (S00)
{
Name (ASUN, Zero)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
Zero,
Zero
}
Local0 [Zero] = BSEL /* \_SB_.PCI0.BSEL */
Local0 [One] = ASUN /* \_SB_.PCI0.S00_.ASUN */
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
Name (_SUN, Zero) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
PCEJ (BSEL, _SUN)
}
}
Scope (S08)
{
Name (ASUN, One)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
Zero,
Zero
}
Local0 [Zero] = BSEL /* \_SB_.PCI0.BSEL */
Local0 [One] = ASUN /* \_SB_.PCI0.S08_.ASUN */
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
Name (_SUN, One) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
PCEJ (BSEL, _SUN)
}
}
Method (DVNT, 2, NotSerialized)
{
If ((Arg0 & One))
{
Notify (S00, Arg1)
}
If ((Arg0 & 0x02))
{
Notify (S08, Arg1)
}
}
Device (PHPR)
{
Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
Name (_STA, 0x0B) // _STA: Status
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x18, // Length
)
})
}
Scope (S38)
{
Method (PCNT, 0, NotSerialized)
{
BNUM = One
DVNT (PCIU, One)
DVNT (PCID, 0x03)
}
}
Method (PCNT, 0, NotSerialized)
{
BNUM = Zero
DVNT (PCIU, One)
DVNT (PCID, 0x03)
^S38.PCNT ()
}
}
}
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
v5 -> v6:
- cropped the commit message
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dc3ab24d05..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpipcihp b/tests/data/acpi/aarch64/virt/DSDT.acpipcihp
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8d55a877a40cb4c4dffdc70378204e12d2261a75 100644
GIT binary patch
literal 6202
zcmb`LOK;oQ6@U+^7e!GrCDWEH%a*2@Oqx!cQdVMn(o7nOlx;bZ%!+m#fI&%T;MR@<
z3^B<RaDxDj2FSSC6l0@Bmnz^NQealI>#mEgyXhb3t||^m+4nTJivh}otou0MJs)|l
zaYfTMx9^q!#6PvRj19ZidTbfBTCFAk0Di~6>hBHViEFo9XIM6LU6<UAj+t#5R!7(M
z6_DJWjtS22uCdjdj177lx?ZnGW0GqO?0i`+zD)xH)1U(UE(wD00RS9>GhAKUHP%Az
zFWS8wUDuaDa_#M=oRM6^XbK@BFXuvpm@Y+;&G@6iB&BYDu%+wzovURpBd->hL5vpH
zSwuZtog#4A_Yfk3s7HtvX0gOW$RdvsXBbN?qrqjwc#I^&Xt0diTt=M7kQl~omT`y6
zNbndk!??pTmbr{1kD)M(WtOqRWu$nF9K%>)8LM1|#AB!oW0hrm!eyj+i~_^>gkjX9
z%|S~{mU#?~VccaI+%lz`WK!z04C7}kgI}i#FOL$#xW_X1b(-Zd$_(REmcg&n9FI|9
z824EQzfPxkj75g=bC$ucQ<cZ4F^mT+gI}k49^(fLqscP(bz0ytK4cgzmcg&nX&&Pv
zhG8&_C4QZ1JjM?hhRHJcbvnai{D@(+Sq8sOXL*btGmJHs!LQRIk8z7(tg{S$otAhE
zondUS41S%?@fb@Cqr)=zbz0^zZZnKcmcg&nc^+e#VLW6R{5q}h7^@7U%QE<Ny1--H
zWf(n%(cstVB9C#8Vf0xBzfP+>#(jpd6)`&T?&X2V>RY;@uU#HKtbv`+$(i7sb1j%3
z9%5*pmUQibEjS@6N{65XiJ(5@pu)aO)Fx&X?H+={!w8$!bq*`+qpWBbQC5tyKH{*#
zzAM(5WptvahODN(iua^rMy&>(`P%Csxvf_J@;=(zgM3x4SYSX0_Mrwk)WC#&_zfJw
zXRr@|kl>hR4YsGdFXWR#CY~9O0iO+o--WKO*P)<bzbxYInKWWuU2i}k8&}3-0WhY1
z*}|wLDCEMiAg*!M#7I4wD+ZBEmo1E(OcldOJ&F_|h@7kv3nC{O#Dd7l)L0l<k0N7X
z<Ybk25IM;p9z;&2#>2=-^6@ZovPyz@CWvQ(dM3ii$tp?WnIxV`>Y1dTDdL$To+;{?
zqMj1*l!&K9JtgXyCZ1{HnWmm;>M0XXnRv?7Q>LC7;+Y|y8S0s#o(l0)h^In573!HK
zo>}6VrJh;pnIoP#;+dnKIqEq@Jg11~6!n~<o+|NFiKj|ERqB~1o_XS#r=EH0Ss<PT
z;#r`c1?o9XJg150H1(XOo*MDgh^Iz9HR?G-JZFgK4E3C$p0mVrmUzxm&spkOB%Vd$
zS)`st>RBS5CE{74o+auzM?B|<=N$E%qn>5rStg!k>RG0q^TczWc+OMLdFojqo)zL*
zp`I1$xj;M@i01<JT%ewd#B-5&E>h1$>RBb8RpMEtp4Ew`rn*L}2^Tqh>w~{<!V}9z
zN`85o1yKRK#`qz8T?A0@We#5Ic>HhtS%#yxzAl2G#KIQ9IG8@Z4<Nw1kC~X@ItgZs
z!%57A{l}nnQ|^{+#NQo(VeZyP{lxh}ep*(Y-rpPls#YHSarb5OFQ5MHSMQGGxMA)t
zy*rX6!`yB7_~E_s<VA0!o}C{GuQ5CrtB<D7&V%8wPsI`6!=67YVHcw67f0GpT+{Bw
zM<0Z1{&nTMf7o|^+xw>Y&)(d(MsJipe+C!%m>}Q>IKy6i(6*VwjS;-U!WUl+S%1$w
zxVz)=xQcg~xm5g)Z^RyCp4`HBZtHE+4c|S4FWl;QNZRR`+4Z(b4wNzBW*B<X9<<j%
z0g%#i+<BA1rqQ<B-J13=;kF-br+sXBBlY~1C*$Gdt+hL7$tR<G*r9@~I@g~3G={6=
zd9Bqo9*)OMhh_A)of}LC&TxivNC{I74~j-~gj3DgKm}pWiDlT^n4OZACFhNbO~W!e
zJ2lJbm^J6bZg0AvNH~t!W7BBq?ai8V((3mHps15jY#OcpPOoNl%*QoHz&t>^ZW--O
z(YY4p?H}L_|5!K#q&PRQ`vSC&n;r8pZx*tA{P3c=o@UCHY4@@tGkN|De0<#AsC>q+
ziwkd*`op0tUU)w2`MAher_TYtI(;s{(^2{C_4!jcf2ssE|9Vf@d%bro$SK(K_f9>4
z3vaY?{!C8&cc5PoMO^cnt7!iz2KZSx^#r)^)CV`hg2B72JxsKNjF-Px!t$Fahf0t`
zAt6E*JU<Y)Owbu-Y+ZLHw`mT*8BW>yYS>V4i#x+L$!=Wrq=3wqT6ViDs9W&>(X@B^
zpxwlMruc=p2;liRArQmCKn?Hx!QrzbPjZ9#1-HGa3;2+6F7{~!^HG0W9A#b|2=Ers
zhrvSd|6VBIt-3+t!uL#E;3ZytFY%G`>OdCJV%0r#hMRF~!x~)es;0gi?SISY)HXhU
z=|BJS*R?P9Uwr=M7oY9FU|yOJ?0i<1*Moo2Lg^UP>-b!>D(+tJ1>6<5IBq>5`eMp4
R?PfR*|6}}@w~&H!{sU733QPb1
literal 0
HcmV?d00001
--
2.49.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v7 00/36] ACPI PCI Hotplug support on ARM
2025-07-14 8:04 [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Eric Auger
` (35 preceding siblings ...)
2025-07-14 8:05 ` [PATCH v7 36/36] qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp Eric Auger
@ 2025-07-14 19:40 ` Jonathan Cameron via
2025-07-14 19:46 ` Eric Auger
2025-07-14 19:51 ` Eric Auger
36 siblings, 2 replies; 52+ messages in thread
From: Jonathan Cameron via @ 2025-07-14 19:40 UTC (permalink / raw)
To: Eric Auger
Cc: eric.auger.pro, qemu-devel, qemu-arm, peter.maydell, imammedo,
gustavo.romero, anisinha, mst, shannon.zhaosl, pbonzini, philmd,
alex.bennee, alireza.sanaee
On Mon, 14 Jul 2025 10:04:44 +0200
Eric Auger <eric.auger@redhat.com> wrote:
> This series enables ACPI PCI hotplug/hotunplug on ARM.
> It is not enabled by default and ACPI PCI hotplug can
> be selected by setting:
>
> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>
> Expected benefits should be similar to those listed in [1],
> ie. removal of some racy behaviors, improved latencies.
>
> The infrastructure used in x86 is heavily reused and a
> huge part of the series consists in moving code from
> hw/i386/acpi-build.c to a generic place and slightly
> adapting it to make it usable on ARM. The DSDT table is
> augmented to support ACPI PCI hotplug elements.
>
> On ARM we use use a GED event to notify the OS about
> hotplug events.
>
> Best Regards
>
> Eric
Hi Eric,
I guess you probably already know this but there is some
impact on loongarch64 when their ACPI tables tests are added.
Rather oddly I'm getting intermittent failures on Michael's
gitlab tree but looks like the unification of _OSC affects
them as well. (should be every time, but they aren't!)
Should just be updating their 4 DSDT variants.
If I had a stable test setup I'd send them. Will try again
tomorrow if not resolved.
Jonathan
>
> This series can be found at:
> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v7
>
> previous series:
> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v6
>
> History:
> v6 -> v7:
> - rebased after minor contextual conflict introduced
> by "hw/arm/virt: Basic CXL enablement on pci_expander_bridge
> instances pxb-cxl" in hw/arm/virt-acpi-build.c
> (hw/pci-host/gpex-acpi: Use GED acpi pcihp property)
> - collected last Igor's and Prasad's R-bs
>
> v5 -> v6:
> - collected Jonathan's R-bs
> - cropped last 2 patch commit messages (Jonathan)
>
> v4 -> v5:
> - Collected Jonathan's R-bs (many thanks!)
> - fixed the tests/qtest/bios-tables-test issue by
> creating a variant for the viot test
> - use the 3 phase reset API
> - fixed qom-test failures that were due to unconditionnal
> fetches of the GED property
>
> v3 -> v4:
> - toook into account all comments on v3
> - static acpi-index is now supported unconditionally
> from acpi pcihp option. See indiviual patches.
> - I hit a problem with ref block generation at
> [19/32] tests/qtest/bios-tables-test: Update ARM DSDT reference
> blobs: despite I regenerate the blobs, I get some errors.
>
> v2 -> v3:
> - lot of changes taking into account various feedbacks
> (many thanks to all reviewers). Please refer to
> individual patches for details. Main changes:
> - no more machine option, acpi pci hp is not set by
> default.
> - removal of 2 unused variables in the osc method
> - introduction of GED property to set the bus
> - rework of the init/reset sequence
> - fix virtio-mem-pci hotplug regression
>
> v1 -> v2:
> - collected a bunch of R-bs from Gustavo (many thanks!)
> - Fixed the breakage of bios-tables-test in TCG mode by
> incorporating Gustavo's patches (part of
> [PATCH 0/5] ACPI tests for PCI Hotplug on ARM
> https://lore.kernel.org/all/20250526053123.1434204-1-gustavo.romero@linaro.org/)
> - Tweeked the dsdt aml changes to avoid any dsdt blob difference when
> acpi-pcihp is off.
>
> RFC -> v1:
> - First 3 trivial patches were pulled separately
> - Fix of the register region size (0x18), ie. ACPI_PCIHP_SIZE
> - addition of aml_pci_edsm which was not called in RFC
> - acpi-index feature is now fixed. vms->bus was not set on
> acpi_pcihp_init. The init sequence is still hacky though. Suggestions
> are welcome.
>
> [1] [PATCH v6 0/6] Use ACPI PCI hot-plug for Q35
> https://lore.kernel.org/all/20210713004205.775386-1-jusual@redhat.com/
>
> Eric Auger (32):
> hw/i386/acpi-build: Make aml_pci_device_dsm() static
> hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
> hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to
> acpi_dsdt_add_pci_osc
> hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
> hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
> hw/pci-host/gpex-acpi: Use GED acpi pcihp property
> hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
> hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
> tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
> hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
> hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
> hw/i386/acpi-build: Move build_append_notification_callback to pcihp
> hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to
> pcihp
> hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
> hw/i386/acpi-build: Move aml_pci_edsm to a generic place
> qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
> qtest/bios-tables-test: Add a variant to the aarch64 viot test
> qtest/bios-tables-test: Generate DSDT.viot
> hw/arm/virt-acpi-build: Let non hotplug ports support static
> acpi-index
> tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
> hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI
> hotplug
> hw/acpi/ged: Add a bus link property
> hw/arm/virt: Pass the bus on the ged creation
> hw/acpi/ged: Call pcihp plug callbacks in hotplug handler
> implementation
> hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
> hw/acpi/ged: Prepare the device to react to PCI hotplug events
> hw/acpi/ged: Support migration of AcpiPciHpState
> hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
> hw/arm/virt: Minor code reshuffling in create_acpi_ged
> hw/arm/virt: Let virt support pci hotplug/unplug GED event
> qtest/bios-tables-test: Generate reference blob for
> DSDT.hpoffacpiindex
> qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
>
> Gustavo Romero (4):
> tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
> tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT
> table
> tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp
> tests
> tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
>
> hw/i386/acpi-build.h | 4 -
> include/hw/acpi/generic_event_device.h | 17 +-
> include/hw/acpi/pci.h | 5 +-
> include/hw/acpi/pcihp.h | 17 +-
> include/hw/arm/virt.h | 1 +
> include/hw/pci-host/gpex.h | 1 +
> include/hw/sysbus.h | 1 +
> hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
> hw/acpi/generic_event_device.c | 77 +++
> hw/acpi/ich9.c | 7 +-
> hw/acpi/pci-bridge.c | 54 ++
> hw/acpi/pci.c | 50 ++
> hw/acpi/pcihp.c | 439 ++++++++++++++-
> hw/acpi/piix4.c | 5 +-
> hw/arm/virt-acpi-build.c | 38 ++
> hw/arm/virt.c | 27 +-
> hw/core/sysbus.c | 11 +
> hw/i386/acpi-build.c | 532 +-----------------
> hw/pci-host/gpex-acpi.c | 74 +--
> tests/qtest/bios-tables-test.c | 53 ++
> hw/arm/Kconfig | 2 +
> hw/pci-host/Kconfig | 1 +
> tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5293 bytes
> .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5379 bytes
> tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
> .../acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
> tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6654 bytes
> tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7768 bytes
> tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5495 bytes
> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5310 bytes
> tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
> tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
> 32 files changed, 811 insertions(+), 607 deletions(-)
> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v7 00/36] ACPI PCI Hotplug support on ARM
2025-07-14 19:40 ` [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Jonathan Cameron via
@ 2025-07-14 19:46 ` Eric Auger
2025-07-14 19:51 ` Eric Auger
1 sibling, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-14 19:46 UTC (permalink / raw)
To: Jonathan Cameron
Cc: eric.auger.pro, qemu-devel, qemu-arm, peter.maydell, imammedo,
gustavo.romero, anisinha, mst, shannon.zhaosl, pbonzini, philmd,
alex.bennee, alireza.sanaee
Hi Jonathan,
On 7/14/25 9:40 PM, Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 10:04:44 +0200
> Eric Auger <eric.auger@redhat.com> wrote:
>
>> This series enables ACPI PCI hotplug/hotunplug on ARM.
>> It is not enabled by default and ACPI PCI hotplug can
>> be selected by setting:
>>
>> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>>
>> Expected benefits should be similar to those listed in [1],
>> ie. removal of some racy behaviors, improved latencies.
>>
>> The infrastructure used in x86 is heavily reused and a
>> huge part of the series consists in moving code from
>> hw/i386/acpi-build.c to a generic place and slightly
>> adapting it to make it usable on ARM. The DSDT table is
>> augmented to support ACPI PCI hotplug elements.
>>
>> On ARM we use use a GED event to notify the OS about
>> hotplug events.
>>
>> Best Regards
>>
>> Eric
> Hi Eric,
>
> I guess you probably already know this but there is some
> impact on loongarch64 when their ACPI tables tests are added.
>
> Rather oddly I'm getting intermittent failures on Michael's
> gitlab tree but looks like the unification of _OSC affects
> them as well. (should be every time, but they aren't!)
>
> Should just be updating their 4 DSDT variants.
thank you for the notice.
I have executed make check with a qemu configured for all archs and I
got not failures.
I guess the tests you are talking about are not merged yet? Anyway I can
add update their DSDT variants once the series is merged.
Thanks
Eric
>
> If I had a stable test setup I'd send them. Will try again
> tomorrow if not resolved.
>
> Jonathan
>
>
>
>> This series can be found at:
>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v7
>>
>> previous series:
>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v6
>>
>> History:
>> v6 -> v7:
>> - rebased after minor contextual conflict introduced
>> by "hw/arm/virt: Basic CXL enablement on pci_expander_bridge
>> instances pxb-cxl" in hw/arm/virt-acpi-build.c
>> (hw/pci-host/gpex-acpi: Use GED acpi pcihp property)
>> - collected last Igor's and Prasad's R-bs
>>
>> v5 -> v6:
>> - collected Jonathan's R-bs
>> - cropped last 2 patch commit messages (Jonathan)
>>
>> v4 -> v5:
>> - Collected Jonathan's R-bs (many thanks!)
>> - fixed the tests/qtest/bios-tables-test issue by
>> creating a variant for the viot test
>> - use the 3 phase reset API
>> - fixed qom-test failures that were due to unconditionnal
>> fetches of the GED property
>>
>> v3 -> v4:
>> - toook into account all comments on v3
>> - static acpi-index is now supported unconditionally
>> from acpi pcihp option. See indiviual patches.
>> - I hit a problem with ref block generation at
>> [19/32] tests/qtest/bios-tables-test: Update ARM DSDT reference
>> blobs: despite I regenerate the blobs, I get some errors.
>>
>> v2 -> v3:
>> - lot of changes taking into account various feedbacks
>> (many thanks to all reviewers). Please refer to
>> individual patches for details. Main changes:
>> - no more machine option, acpi pci hp is not set by
>> default.
>> - removal of 2 unused variables in the osc method
>> - introduction of GED property to set the bus
>> - rework of the init/reset sequence
>> - fix virtio-mem-pci hotplug regression
>>
>> v1 -> v2:
>> - collected a bunch of R-bs from Gustavo (many thanks!)
>> - Fixed the breakage of bios-tables-test in TCG mode by
>> incorporating Gustavo's patches (part of
>> [PATCH 0/5] ACPI tests for PCI Hotplug on ARM
>> https://lore.kernel.org/all/20250526053123.1434204-1-gustavo.romero@linaro.org/)
>> - Tweeked the dsdt aml changes to avoid any dsdt blob difference when
>> acpi-pcihp is off.
>>
>> RFC -> v1:
>> - First 3 trivial patches were pulled separately
>> - Fix of the register region size (0x18), ie. ACPI_PCIHP_SIZE
>> - addition of aml_pci_edsm which was not called in RFC
>> - acpi-index feature is now fixed. vms->bus was not set on
>> acpi_pcihp_init. The init sequence is still hacky though. Suggestions
>> are welcome.
>>
>> [1] [PATCH v6 0/6] Use ACPI PCI hot-plug for Q35
>> https://lore.kernel.org/all/20210713004205.775386-1-jusual@redhat.com/
>>
>> Eric Auger (32):
>> hw/i386/acpi-build: Make aml_pci_device_dsm() static
>> hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
>> hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to
>> acpi_dsdt_add_pci_osc
>> hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
>> hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
>> hw/pci-host/gpex-acpi: Use GED acpi pcihp property
>> hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
>> hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
>> tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
>> hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
>> hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
>> hw/i386/acpi-build: Move build_append_notification_callback to pcihp
>> hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to
>> pcihp
>> hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
>> hw/i386/acpi-build: Move aml_pci_edsm to a generic place
>> qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
>> qtest/bios-tables-test: Add a variant to the aarch64 viot test
>> qtest/bios-tables-test: Generate DSDT.viot
>> hw/arm/virt-acpi-build: Let non hotplug ports support static
>> acpi-index
>> tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
>> hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI
>> hotplug
>> hw/acpi/ged: Add a bus link property
>> hw/arm/virt: Pass the bus on the ged creation
>> hw/acpi/ged: Call pcihp plug callbacks in hotplug handler
>> implementation
>> hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
>> hw/acpi/ged: Prepare the device to react to PCI hotplug events
>> hw/acpi/ged: Support migration of AcpiPciHpState
>> hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
>> hw/arm/virt: Minor code reshuffling in create_acpi_ged
>> hw/arm/virt: Let virt support pci hotplug/unplug GED event
>> qtest/bios-tables-test: Generate reference blob for
>> DSDT.hpoffacpiindex
>> qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
>>
>> Gustavo Romero (4):
>> tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
>> tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT
>> table
>> tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp
>> tests
>> tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
>>
>> hw/i386/acpi-build.h | 4 -
>> include/hw/acpi/generic_event_device.h | 17 +-
>> include/hw/acpi/pci.h | 5 +-
>> include/hw/acpi/pcihp.h | 17 +-
>> include/hw/arm/virt.h | 1 +
>> include/hw/pci-host/gpex.h | 1 +
>> include/hw/sysbus.h | 1 +
>> hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
>> hw/acpi/generic_event_device.c | 77 +++
>> hw/acpi/ich9.c | 7 +-
>> hw/acpi/pci-bridge.c | 54 ++
>> hw/acpi/pci.c | 50 ++
>> hw/acpi/pcihp.c | 439 ++++++++++++++-
>> hw/acpi/piix4.c | 5 +-
>> hw/arm/virt-acpi-build.c | 38 ++
>> hw/arm/virt.c | 27 +-
>> hw/core/sysbus.c | 11 +
>> hw/i386/acpi-build.c | 532 +-----------------
>> hw/pci-host/gpex-acpi.c | 74 +--
>> tests/qtest/bios-tables-test.c | 53 ++
>> hw/arm/Kconfig | 2 +
>> hw/pci-host/Kconfig | 1 +
>> tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5293 bytes
>> .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5379 bytes
>> tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
>> .../acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
>> tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6654 bytes
>> tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7768 bytes
>> tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5495 bytes
>> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5310 bytes
>> tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
>> tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
>> 32 files changed, 811 insertions(+), 607 deletions(-)
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
>>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 00/36] ACPI PCI Hotplug support on ARM
2025-07-14 19:40 ` [PATCH v7 00/36] ACPI PCI Hotplug support on ARM Jonathan Cameron via
2025-07-14 19:46 ` Eric Auger
@ 2025-07-14 19:51 ` Eric Auger
2025-07-14 23:56 ` Michael S. Tsirkin
1 sibling, 1 reply; 52+ messages in thread
From: Eric Auger @ 2025-07-14 19:51 UTC (permalink / raw)
To: Jonathan Cameron
Cc: eric.auger.pro, qemu-devel, qemu-arm, peter.maydell, imammedo,
gustavo.romero, anisinha, mst, shannon.zhaosl, pbonzini, philmd,
alex.bennee, alireza.sanaee
Hi Jonathan,
On 7/14/25 9:40 PM, Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 10:04:44 +0200
> Eric Auger <eric.auger@redhat.com> wrote:
>
>> This series enables ACPI PCI hotplug/hotunplug on ARM.
>> It is not enabled by default and ACPI PCI hotplug can
>> be selected by setting:
>>
>> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>>
>> Expected benefits should be similar to those listed in [1],
>> ie. removal of some racy behaviors, improved latencies.
>>
>> The infrastructure used in x86 is heavily reused and a
>> huge part of the series consists in moving code from
>> hw/i386/acpi-build.c to a generic place and slightly
>> adapting it to make it usable on ARM. The DSDT table is
>> augmented to support ACPI PCI hotplug elements.
>>
>> On ARM we use use a GED event to notify the OS about
>> hotplug events.
>>
>> Best Regards
>>
>> Eric
> Hi Eric,
>
> I guess you probably already know this but there is some
> impact on loongarch64 when their ACPI tables tests are added.
>
> Rather oddly I'm getting intermittent failures on Michael's
> gitlab tree but looks like the unification of _OSC affects
> them as well. (should be every time, but they aren't!)
>
> Should just be updating their 4 DSDT variants.
>
> If I had a stable test setup I'd send them. Will try again
> tomorrow if not resolved.
just to make sure are we talking about
[PATCH v3 0/5] Add bios-tables-test for LoongArch system <https://lore.kernel.org/all/20250612090321.3416594-1-maobibo@loongson.cn/>
https://lore.kernel.org/all/20250612090321.3416594-2-maobibo@loongson.cn/
Thanks
Eric
>
> Jonathan
>
>
>
>> This series can be found at:
>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v7
>>
>> previous series:
>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v6
>>
>> History:
>> v6 -> v7:
>> - rebased after minor contextual conflict introduced
>> by "hw/arm/virt: Basic CXL enablement on pci_expander_bridge
>> instances pxb-cxl" in hw/arm/virt-acpi-build.c
>> (hw/pci-host/gpex-acpi: Use GED acpi pcihp property)
>> - collected last Igor's and Prasad's R-bs
>>
>> v5 -> v6:
>> - collected Jonathan's R-bs
>> - cropped last 2 patch commit messages (Jonathan)
>>
>> v4 -> v5:
>> - Collected Jonathan's R-bs (many thanks!)
>> - fixed the tests/qtest/bios-tables-test issue by
>> creating a variant for the viot test
>> - use the 3 phase reset API
>> - fixed qom-test failures that were due to unconditionnal
>> fetches of the GED property
>>
>> v3 -> v4:
>> - toook into account all comments on v3
>> - static acpi-index is now supported unconditionally
>> from acpi pcihp option. See indiviual patches.
>> - I hit a problem with ref block generation at
>> [19/32] tests/qtest/bios-tables-test: Update ARM DSDT reference
>> blobs: despite I regenerate the blobs, I get some errors.
>>
>> v2 -> v3:
>> - lot of changes taking into account various feedbacks
>> (many thanks to all reviewers). Please refer to
>> individual patches for details. Main changes:
>> - no more machine option, acpi pci hp is not set by
>> default.
>> - removal of 2 unused variables in the osc method
>> - introduction of GED property to set the bus
>> - rework of the init/reset sequence
>> - fix virtio-mem-pci hotplug regression
>>
>> v1 -> v2:
>> - collected a bunch of R-bs from Gustavo (many thanks!)
>> - Fixed the breakage of bios-tables-test in TCG mode by
>> incorporating Gustavo's patches (part of
>> [PATCH 0/5] ACPI tests for PCI Hotplug on ARM
>> https://lore.kernel.org/all/20250526053123.1434204-1-gustavo.romero@linaro.org/)
>> - Tweeked the dsdt aml changes to avoid any dsdt blob difference when
>> acpi-pcihp is off.
>>
>> RFC -> v1:
>> - First 3 trivial patches were pulled separately
>> - Fix of the register region size (0x18), ie. ACPI_PCIHP_SIZE
>> - addition of aml_pci_edsm which was not called in RFC
>> - acpi-index feature is now fixed. vms->bus was not set on
>> acpi_pcihp_init. The init sequence is still hacky though. Suggestions
>> are welcome.
>>
>> [1] [PATCH v6 0/6] Use ACPI PCI hot-plug for Q35
>> https://lore.kernel.org/all/20210713004205.775386-1-jusual@redhat.com/
>>
>> Eric Auger (32):
>> hw/i386/acpi-build: Make aml_pci_device_dsm() static
>> hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
>> hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to
>> acpi_dsdt_add_pci_osc
>> hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
>> hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
>> hw/pci-host/gpex-acpi: Use GED acpi pcihp property
>> hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
>> hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
>> tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
>> hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
>> hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
>> hw/i386/acpi-build: Move build_append_notification_callback to pcihp
>> hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to
>> pcihp
>> hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
>> hw/i386/acpi-build: Move aml_pci_edsm to a generic place
>> qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
>> qtest/bios-tables-test: Add a variant to the aarch64 viot test
>> qtest/bios-tables-test: Generate DSDT.viot
>> hw/arm/virt-acpi-build: Let non hotplug ports support static
>> acpi-index
>> tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
>> hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI
>> hotplug
>> hw/acpi/ged: Add a bus link property
>> hw/arm/virt: Pass the bus on the ged creation
>> hw/acpi/ged: Call pcihp plug callbacks in hotplug handler
>> implementation
>> hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
>> hw/acpi/ged: Prepare the device to react to PCI hotplug events
>> hw/acpi/ged: Support migration of AcpiPciHpState
>> hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
>> hw/arm/virt: Minor code reshuffling in create_acpi_ged
>> hw/arm/virt: Let virt support pci hotplug/unplug GED event
>> qtest/bios-tables-test: Generate reference blob for
>> DSDT.hpoffacpiindex
>> qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
>>
>> Gustavo Romero (4):
>> tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
>> tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT
>> table
>> tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp
>> tests
>> tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
>>
>> hw/i386/acpi-build.h | 4 -
>> include/hw/acpi/generic_event_device.h | 17 +-
>> include/hw/acpi/pci.h | 5 +-
>> include/hw/acpi/pcihp.h | 17 +-
>> include/hw/arm/virt.h | 1 +
>> include/hw/pci-host/gpex.h | 1 +
>> include/hw/sysbus.h | 1 +
>> hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
>> hw/acpi/generic_event_device.c | 77 +++
>> hw/acpi/ich9.c | 7 +-
>> hw/acpi/pci-bridge.c | 54 ++
>> hw/acpi/pci.c | 50 ++
>> hw/acpi/pcihp.c | 439 ++++++++++++++-
>> hw/acpi/piix4.c | 5 +-
>> hw/arm/virt-acpi-build.c | 38 ++
>> hw/arm/virt.c | 27 +-
>> hw/core/sysbus.c | 11 +
>> hw/i386/acpi-build.c | 532 +-----------------
>> hw/pci-host/gpex-acpi.c | 74 +--
>> tests/qtest/bios-tables-test.c | 53 ++
>> hw/arm/Kconfig | 2 +
>> hw/pci-host/Kconfig | 1 +
>> tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5293 bytes
>> .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5379 bytes
>> tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
>> .../acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
>> tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6654 bytes
>> tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7768 bytes
>> tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5495 bytes
>> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5310 bytes
>> tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
>> tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
>> 32 files changed, 811 insertions(+), 607 deletions(-)
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
>>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 00/36] ACPI PCI Hotplug support on ARM
2025-07-14 19:51 ` Eric Auger
@ 2025-07-14 23:56 ` Michael S. Tsirkin
2025-07-15 8:53 ` Eric Auger
0 siblings, 1 reply; 52+ messages in thread
From: Michael S. Tsirkin @ 2025-07-14 23:56 UTC (permalink / raw)
To: Eric Auger
Cc: Jonathan Cameron, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, gustavo.romero, anisinha, shannon.zhaosl,
pbonzini, philmd, alex.bennee, alireza.sanaee
On Mon, Jul 14, 2025 at 09:51:40PM +0200, Eric Auger wrote:
> Hi Jonathan,
>
> On 7/14/25 9:40 PM, Jonathan Cameron wrote:
> > On Mon, 14 Jul 2025 10:04:44 +0200
> > Eric Auger <eric.auger@redhat.com> wrote:
> >
> >> This series enables ACPI PCI hotplug/hotunplug on ARM.
> >> It is not enabled by default and ACPI PCI hotplug can
> >> be selected by setting:
> >>
> >> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
> >>
> >> Expected benefits should be similar to those listed in [1],
> >> ie. removal of some racy behaviors, improved latencies.
> >>
> >> The infrastructure used in x86 is heavily reused and a
> >> huge part of the series consists in moving code from
> >> hw/i386/acpi-build.c to a generic place and slightly
> >> adapting it to make it usable on ARM. The DSDT table is
> >> augmented to support ACPI PCI hotplug elements.
> >>
> >> On ARM we use use a GED event to notify the OS about
> >> hotplug events.
> >>
> >> Best Regards
> >>
> >> Eric
> > Hi Eric,
> >
> > I guess you probably already know this but there is some
> > impact on loongarch64 when their ACPI tables tests are added.
> >
> > Rather oddly I'm getting intermittent failures on Michael's
> > gitlab tree but looks like the unification of _OSC affects
> > them as well. (should be every time, but they aren't!)
> >
> > Should just be updating their 4 DSDT variants.
> >
> > If I had a stable test setup I'd send them. Will try again
> > tomorrow if not resolved.
> just to make sure are we talking about
>
> [PATCH v3 0/5] Add bios-tables-test for LoongArch system <https://lore.kernel.org/all/20250612090321.3416594-1-maobibo@loongson.cn/>
> https://lore.kernel.org/all/20250612090321.3416594-2-maobibo@loongson.cn/
>
> Thanks
>
> Eric
I fixed this up, don't worry.
>
>
> >
> > Jonathan
> >
> >
> >
> >> This series can be found at:
> >> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v7
> >>
> >> previous series:
> >> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v6
> >>
> >> History:
> >> v6 -> v7:
> >> - rebased after minor contextual conflict introduced
> >> by "hw/arm/virt: Basic CXL enablement on pci_expander_bridge
> >> instances pxb-cxl" in hw/arm/virt-acpi-build.c
> >> (hw/pci-host/gpex-acpi: Use GED acpi pcihp property)
> >> - collected last Igor's and Prasad's R-bs
> >>
> >> v5 -> v6:
> >> - collected Jonathan's R-bs
> >> - cropped last 2 patch commit messages (Jonathan)
> >>
> >> v4 -> v5:
> >> - Collected Jonathan's R-bs (many thanks!)
> >> - fixed the tests/qtest/bios-tables-test issue by
> >> creating a variant for the viot test
> >> - use the 3 phase reset API
> >> - fixed qom-test failures that were due to unconditionnal
> >> fetches of the GED property
> >>
> >> v3 -> v4:
> >> - toook into account all comments on v3
> >> - static acpi-index is now supported unconditionally
> >> from acpi pcihp option. See indiviual patches.
> >> - I hit a problem with ref block generation at
> >> [19/32] tests/qtest/bios-tables-test: Update ARM DSDT reference
> >> blobs: despite I regenerate the blobs, I get some errors.
> >>
> >> v2 -> v3:
> >> - lot of changes taking into account various feedbacks
> >> (many thanks to all reviewers). Please refer to
> >> individual patches for details. Main changes:
> >> - no more machine option, acpi pci hp is not set by
> >> default.
> >> - removal of 2 unused variables in the osc method
> >> - introduction of GED property to set the bus
> >> - rework of the init/reset sequence
> >> - fix virtio-mem-pci hotplug regression
> >>
> >> v1 -> v2:
> >> - collected a bunch of R-bs from Gustavo (many thanks!)
> >> - Fixed the breakage of bios-tables-test in TCG mode by
> >> incorporating Gustavo's patches (part of
> >> [PATCH 0/5] ACPI tests for PCI Hotplug on ARM
> >> https://lore.kernel.org/all/20250526053123.1434204-1-gustavo.romero@linaro.org/)
> >> - Tweeked the dsdt aml changes to avoid any dsdt blob difference when
> >> acpi-pcihp is off.
> >>
> >> RFC -> v1:
> >> - First 3 trivial patches were pulled separately
> >> - Fix of the register region size (0x18), ie. ACPI_PCIHP_SIZE
> >> - addition of aml_pci_edsm which was not called in RFC
> >> - acpi-index feature is now fixed. vms->bus was not set on
> >> acpi_pcihp_init. The init sequence is still hacky though. Suggestions
> >> are welcome.
> >>
> >> [1] [PATCH v6 0/6] Use ACPI PCI hot-plug for Q35
> >> https://lore.kernel.org/all/20210713004205.775386-1-jusual@redhat.com/
> >>
> >> Eric Auger (32):
> >> hw/i386/acpi-build: Make aml_pci_device_dsm() static
> >> hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
> >> hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to
> >> acpi_dsdt_add_pci_osc
> >> hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
> >> hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
> >> hw/pci-host/gpex-acpi: Use GED acpi pcihp property
> >> hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
> >> hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
> >> tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
> >> hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
> >> hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
> >> hw/i386/acpi-build: Move build_append_notification_callback to pcihp
> >> hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to
> >> pcihp
> >> hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
> >> hw/i386/acpi-build: Move aml_pci_edsm to a generic place
> >> qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
> >> qtest/bios-tables-test: Add a variant to the aarch64 viot test
> >> qtest/bios-tables-test: Generate DSDT.viot
> >> hw/arm/virt-acpi-build: Let non hotplug ports support static
> >> acpi-index
> >> tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
> >> hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI
> >> hotplug
> >> hw/acpi/ged: Add a bus link property
> >> hw/arm/virt: Pass the bus on the ged creation
> >> hw/acpi/ged: Call pcihp plug callbacks in hotplug handler
> >> implementation
> >> hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
> >> hw/acpi/ged: Prepare the device to react to PCI hotplug events
> >> hw/acpi/ged: Support migration of AcpiPciHpState
> >> hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
> >> hw/arm/virt: Minor code reshuffling in create_acpi_ged
> >> hw/arm/virt: Let virt support pci hotplug/unplug GED event
> >> qtest/bios-tables-test: Generate reference blob for
> >> DSDT.hpoffacpiindex
> >> qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
> >>
> >> Gustavo Romero (4):
> >> tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
> >> tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT
> >> table
> >> tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp
> >> tests
> >> tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
> >>
> >> hw/i386/acpi-build.h | 4 -
> >> include/hw/acpi/generic_event_device.h | 17 +-
> >> include/hw/acpi/pci.h | 5 +-
> >> include/hw/acpi/pcihp.h | 17 +-
> >> include/hw/arm/virt.h | 1 +
> >> include/hw/pci-host/gpex.h | 1 +
> >> include/hw/sysbus.h | 1 +
> >> hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
> >> hw/acpi/generic_event_device.c | 77 +++
> >> hw/acpi/ich9.c | 7 +-
> >> hw/acpi/pci-bridge.c | 54 ++
> >> hw/acpi/pci.c | 50 ++
> >> hw/acpi/pcihp.c | 439 ++++++++++++++-
> >> hw/acpi/piix4.c | 5 +-
> >> hw/arm/virt-acpi-build.c | 38 ++
> >> hw/arm/virt.c | 27 +-
> >> hw/core/sysbus.c | 11 +
> >> hw/i386/acpi-build.c | 532 +-----------------
> >> hw/pci-host/gpex-acpi.c | 74 +--
> >> tests/qtest/bios-tables-test.c | 53 ++
> >> hw/arm/Kconfig | 2 +
> >> hw/pci-host/Kconfig | 1 +
> >> tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5293 bytes
> >> .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5379 bytes
> >> tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
> >> .../acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
> >> tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6654 bytes
> >> tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7768 bytes
> >> tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5495 bytes
> >> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5310 bytes
> >> tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
> >> tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
> >> 32 files changed, 811 insertions(+), 607 deletions(-)
> >> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
> >> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
> >> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
> >>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v7 00/36] ACPI PCI Hotplug support on ARM
2025-07-14 23:56 ` Michael S. Tsirkin
@ 2025-07-15 8:53 ` Eric Auger
0 siblings, 0 replies; 52+ messages in thread
From: Eric Auger @ 2025-07-15 8:53 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Jonathan Cameron, eric.auger.pro, qemu-devel, qemu-arm,
peter.maydell, imammedo, gustavo.romero, anisinha, shannon.zhaosl,
pbonzini, philmd, alex.bennee, alireza.sanaee
On 7/15/25 1:56 AM, Michael S. Tsirkin wrote:
> On Mon, Jul 14, 2025 at 09:51:40PM +0200, Eric Auger wrote:
>> Hi Jonathan,
>>
>> On 7/14/25 9:40 PM, Jonathan Cameron wrote:
>>> On Mon, 14 Jul 2025 10:04:44 +0200
>>> Eric Auger <eric.auger@redhat.com> wrote:
>>>
>>>> This series enables ACPI PCI hotplug/hotunplug on ARM.
>>>> It is not enabled by default and ACPI PCI hotplug can
>>>> be selected by setting:
>>>>
>>>> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>>>>
>>>> Expected benefits should be similar to those listed in [1],
>>>> ie. removal of some racy behaviors, improved latencies.
>>>>
>>>> The infrastructure used in x86 is heavily reused and a
>>>> huge part of the series consists in moving code from
>>>> hw/i386/acpi-build.c to a generic place and slightly
>>>> adapting it to make it usable on ARM. The DSDT table is
>>>> augmented to support ACPI PCI hotplug elements.
>>>>
>>>> On ARM we use use a GED event to notify the OS about
>>>> hotplug events.
>>>>
>>>> Best Regards
>>>>
>>>> Eric
>>> Hi Eric,
>>>
>>> I guess you probably already know this but there is some
>>> impact on loongarch64 when their ACPI tables tests are added.
>>>
>>> Rather oddly I'm getting intermittent failures on Michael's
>>> gitlab tree but looks like the unification of _OSC affects
>>> them as well. (should be every time, but they aren't!)
>>>
>>> Should just be updating their 4 DSDT variants.
>>>
>>> If I had a stable test setup I'd send them. Will try again
>>> tomorrow if not resolved.
>> just to make sure are we talking about
>>
>> [PATCH v3 0/5] Add bios-tables-test for LoongArch system <https://lore.kernel.org/all/20250612090321.3416594-1-maobibo@loongson.cn/>
>> https://lore.kernel.org/all/20250612090321.3416594-2-maobibo@loongson.cn/
>>
>> Thanks
>>
>> Eric
> I fixed this up, don't worry.
Thanks!
Eric
>
>>
>>> Jonathan
>>>
>>>
>>>
>>>> This series can be found at:
>>>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v7
>>>>
>>>> previous series:
>>>> https://github.com/eauger/qemu/tree/arm-acpi-pcihp-v6
>>>>
>>>> History:
>>>> v6 -> v7:
>>>> - rebased after minor contextual conflict introduced
>>>> by "hw/arm/virt: Basic CXL enablement on pci_expander_bridge
>>>> instances pxb-cxl" in hw/arm/virt-acpi-build.c
>>>> (hw/pci-host/gpex-acpi: Use GED acpi pcihp property)
>>>> - collected last Igor's and Prasad's R-bs
>>>>
>>>> v5 -> v6:
>>>> - collected Jonathan's R-bs
>>>> - cropped last 2 patch commit messages (Jonathan)
>>>>
>>>> v4 -> v5:
>>>> - Collected Jonathan's R-bs (many thanks!)
>>>> - fixed the tests/qtest/bios-tables-test issue by
>>>> creating a variant for the viot test
>>>> - use the 3 phase reset API
>>>> - fixed qom-test failures that were due to unconditionnal
>>>> fetches of the GED property
>>>>
>>>> v3 -> v4:
>>>> - toook into account all comments on v3
>>>> - static acpi-index is now supported unconditionally
>>>> from acpi pcihp option. See indiviual patches.
>>>> - I hit a problem with ref block generation at
>>>> [19/32] tests/qtest/bios-tables-test: Update ARM DSDT reference
>>>> blobs: despite I regenerate the blobs, I get some errors.
>>>>
>>>> v2 -> v3:
>>>> - lot of changes taking into account various feedbacks
>>>> (many thanks to all reviewers). Please refer to
>>>> individual patches for details. Main changes:
>>>> - no more machine option, acpi pci hp is not set by
>>>> default.
>>>> - removal of 2 unused variables in the osc method
>>>> - introduction of GED property to set the bus
>>>> - rework of the init/reset sequence
>>>> - fix virtio-mem-pci hotplug regression
>>>>
>>>> v1 -> v2:
>>>> - collected a bunch of R-bs from Gustavo (many thanks!)
>>>> - Fixed the breakage of bios-tables-test in TCG mode by
>>>> incorporating Gustavo's patches (part of
>>>> [PATCH 0/5] ACPI tests for PCI Hotplug on ARM
>>>> https://lore.kernel.org/all/20250526053123.1434204-1-gustavo.romero@linaro.org/)
>>>> - Tweeked the dsdt aml changes to avoid any dsdt blob difference when
>>>> acpi-pcihp is off.
>>>>
>>>> RFC -> v1:
>>>> - First 3 trivial patches were pulled separately
>>>> - Fix of the register region size (0x18), ie. ACPI_PCIHP_SIZE
>>>> - addition of aml_pci_edsm which was not called in RFC
>>>> - acpi-index feature is now fixed. vms->bus was not set on
>>>> acpi_pcihp_init. The init sequence is still hacky though. Suggestions
>>>> are welcome.
>>>>
>>>> [1] [PATCH v6 0/6] Use ACPI PCI hot-plug for Q35
>>>> https://lore.kernel.org/all/20210713004205.775386-1-jusual@redhat.com/
>>>>
>>>> Eric Auger (32):
>>>> hw/i386/acpi-build: Make aml_pci_device_dsm() static
>>>> hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp
>>>> hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to
>>>> acpi_dsdt_add_pci_osc
>>>> hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation
>>>> hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property
>>>> hw/pci-host/gpex-acpi: Use GED acpi pcihp property
>>>> hw/i386/acpi-build: Turn build_q35_osc_method into a generic method
>>>> hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method
>>>> tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _OSC change
>>>> hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper
>>>> hw/acpi/pcihp: Add an AmlRegionSpace arg to build_acpi_pci_hotplug
>>>> hw/i386/acpi-build: Move build_append_notification_callback to pcihp
>>>> hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to
>>>> pcihp
>>>> hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info
>>>> hw/i386/acpi-build: Move aml_pci_edsm to a generic place
>>>> qtest/bios-tables-test: Prepare for fixing the aarch64 viot test
>>>> qtest/bios-tables-test: Add a variant to the aarch64 viot test
>>>> qtest/bios-tables-test: Generate DSDT.viot
>>>> hw/arm/virt-acpi-build: Let non hotplug ports support static
>>>> acpi-index
>>>> tests/qtest/bios-tables-test: Update ARM DSDT reference blobs
>>>> hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI
>>>> hotplug
>>>> hw/acpi/ged: Add a bus link property
>>>> hw/arm/virt: Pass the bus on the ged creation
>>>> hw/acpi/ged: Call pcihp plug callbacks in hotplug handler
>>>> implementation
>>>> hw/acpi/pcihp: Remove root arg in acpi_pcihp_init
>>>> hw/acpi/ged: Prepare the device to react to PCI hotplug events
>>>> hw/acpi/ged: Support migration of AcpiPciHpState
>>>> hw/core/sysbus: Introduce sysbus_mmio_map_name() helper
>>>> hw/arm/virt: Minor code reshuffling in create_acpi_ged
>>>> hw/arm/virt: Let virt support pci hotplug/unplug GED event
>>>> qtest/bios-tables-test: Generate reference blob for
>>>> DSDT.hpoffacpiindex
>>>> qtest/bios-tables-test: Generate reference blob for DSDT.acpipcihp
>>>>
>>>> Gustavo Romero (4):
>>>> tests/qtest/bios-tables-test: Prepare for changes in the DSDT table
>>>> tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT
>>>> table
>>>> tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp
>>>> tests
>>>> tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test
>>>>
>>>> hw/i386/acpi-build.h | 4 -
>>>> include/hw/acpi/generic_event_device.h | 17 +-
>>>> include/hw/acpi/pci.h | 5 +-
>>>> include/hw/acpi/pcihp.h | 17 +-
>>>> include/hw/arm/virt.h | 1 +
>>>> include/hw/pci-host/gpex.h | 1 +
>>>> include/hw/sysbus.h | 1 +
>>>> hw/acpi/acpi-pci-hotplug-stub.c | 2 +-
>>>> hw/acpi/generic_event_device.c | 77 +++
>>>> hw/acpi/ich9.c | 7 +-
>>>> hw/acpi/pci-bridge.c | 54 ++
>>>> hw/acpi/pci.c | 50 ++
>>>> hw/acpi/pcihp.c | 439 ++++++++++++++-
>>>> hw/acpi/piix4.c | 5 +-
>>>> hw/arm/virt-acpi-build.c | 38 ++
>>>> hw/arm/virt.c | 27 +-
>>>> hw/core/sysbus.c | 11 +
>>>> hw/i386/acpi-build.c | 532 +-----------------
>>>> hw/pci-host/gpex-acpi.c | 74 +--
>>>> tests/qtest/bios-tables-test.c | 53 ++
>>>> hw/arm/Kconfig | 2 +
>>>> hw/pci-host/Kconfig | 1 +
>>>> tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5293 bytes
>>>> .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5379 bytes
>>>> tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes
>>>> .../acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes
>>>> tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6654 bytes
>>>> tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7768 bytes
>>>> tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5495 bytes
>>>> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5310 bytes
>>>> tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes
>>>> tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes
>>>> 32 files changed, 811 insertions(+), 607 deletions(-)
>>>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp
>>>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
>>>> create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot
>>>>
^ permalink raw reply [flat|nested] 52+ messages in thread