From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Yi Lai <yi1.lai@intel.com>
Subject: [PULL 41/77] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding
Date: Mon, 14 Jul 2025 13:03:30 +0200 [thread overview]
Message-ID: <20250714110406.117772-42-pbonzini@redhat.com> (raw)
In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com>
From: Zhao Liu <zhao1.liu@intel.com>
The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative,
64 byte line size) corresponds to descriptor 0x49, but at present
cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has
multiple meanings.
The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent
cache model, and use legacy_l2_cache as the default L2 cache.
Therefore, add descriptor 0x49 to represent general L2 cache.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250711102143.1622339-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f107e586734..4386b60ff6c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -129,7 +129,18 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
.associativity = 8, .line_size = 64, },
[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
.associativity = 12, .line_size = 64, },
- /* Descriptor 0x49 depends on CPU family/model, so it is not included */
+ /*
+ * Descriptor 0x49 has 2 cases:
+ * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
+ * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
+ * (Intel Xeon processor MP, Family 0FH, Model 06H).
+ *
+ * When it represents L3, then it depends on CPU family/model. Fortunately,
+ * the legacy cache/CPU models don't have such special L3. So, just add it
+ * to represent the general L2 case.
+ */
+ [0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB,
+ .associativity = 16, .line_size = 64, },
[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 12, .line_size = 64, },
[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
--
2.50.0
next prev parent reply other threads:[~2025-07-14 11:19 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 11:02 [PULL 00/77] Rust, target/i386 changes for QEMU 10.1 soft freeze Paolo Bonzini
2025-07-14 11:02 ` [PULL 01/77] rust/qemu-api: Fix binding path in source directory Paolo Bonzini
2025-07-14 11:02 ` [PULL 02/77] rust/qemu-api-macros: use syn::Error directly Paolo Bonzini
2025-07-14 11:02 ` [PULL 03/77] rust/bindings: allow unnecessary_transmutes (1.88) Paolo Bonzini
2025-07-14 11:02 ` [PULL 04/77] rust/qemu-api-macros: normalize TryInto output Paolo Bonzini
2025-07-14 11:02 ` [PULL 05/77] rust/qemu-api-macros: add unit tests Paolo Bonzini
2025-07-14 11:02 ` [PULL 06/77] rust/qemu-api: log: implement io::Write Paolo Bonzini
2025-07-14 11:02 ` [PULL 07/77] target/i386: move max_features to class Paolo Bonzini
2025-07-14 11:02 ` [PULL 08/77] target/i386: nvmm, whpx: add accel/CPU class that sets host vendor Paolo Bonzini
2025-07-14 11:02 ` [PULL 09/77] target/i386: allow reordering max_x86_cpu_initfn vs accel CPU init Paolo Bonzini
2025-07-14 11:02 ` [PULL 10/77] target/i386: move accel_cpu_instance_init to .instance_init Paolo Bonzini
2025-07-14 11:03 ` [PULL 11/77] target/i386: merge host_cpu_instance_init() and host_cpu_max_instance_init() Paolo Bonzini
2025-07-14 11:03 ` [PULL 12/77] i386/tdx: Remove enumeration of GetQuote in tdx_handle_get_tdvmcall_info() Paolo Bonzini
2025-07-14 11:03 ` [PULL 13/77] update Linux headers to KVM tree master Paolo Bonzini
2025-07-14 11:03 ` [PULL 14/77] i386/tdx: Set value of <GetTdVmCallInfo> based on capabilities of both KVM and QEMU Paolo Bonzini
2025-07-14 11:03 ` [PULL 15/77] i386/tdx: handle TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT Paolo Bonzini
2025-07-17 9:46 ` Peter Maydell
2025-07-17 10:19 ` Xiaoyao Li
2025-07-14 11:03 ` [PULL 16/77] i386/tdx: Fix the report of gpa in QAPI Paolo Bonzini
2025-07-14 11:03 ` [PULL 17/77] meson: Add optional dependency on IGVM library Paolo Bonzini
2025-07-16 11:31 ` Daniel P. Berrangé
2025-07-17 13:30 ` Stefano Garzarella
2025-07-17 13:33 ` Daniel P. Berrangé
2025-07-17 15:47 ` Peter Maydell
2025-07-14 11:03 ` [PULL 18/77] backends/confidential-guest-support: Add functions to support IGVM Paolo Bonzini
2025-07-14 11:03 ` [PULL 19/77] backends/igvm: Add IGVM loader and configuration Paolo Bonzini
2025-07-14 11:03 ` [PULL 20/77] hw/i386: Add igvm-cfg object and processing for IGVM files Paolo Bonzini
2025-07-14 11:03 ` [PULL 21/77] i386/pc_sysfw: Ensure sysfw flash configuration does not conflict with IGVM Paolo Bonzini
2025-07-14 11:03 ` [PULL 22/77] sev: Update launch_update_data functions to use Error handling Paolo Bonzini
2025-07-14 11:03 ` [PULL 23/77] target/i386: Allow setting of R_LDTR and R_TR with cpu_x86_load_seg_cache() Paolo Bonzini
2025-07-14 11:03 ` [PULL 24/77] i386/sev: Refactor setting of reset vector and initial CPU state Paolo Bonzini
2025-07-14 11:03 ` [PULL 25/77] i386/sev: Implement ConfidentialGuestSupport functions for SEV Paolo Bonzini
2025-07-14 11:03 ` [PULL 26/77] docs/system: Add documentation on support for IGVM Paolo Bonzini
2025-07-14 11:03 ` [PULL 27/77] docs/interop/firmware.json: Add igvm to FirmwareDevice Paolo Bonzini
2025-07-14 11:03 ` [PULL 28/77] backends/confidential-guest-support: Add set_guest_policy() function Paolo Bonzini
2025-07-14 11:03 ` [PULL 29/77] backends/igvm: Process initialization sections in IGVM file Paolo Bonzini
2025-07-14 11:03 ` [PULL 30/77] backends/igvm: Handle policy for SEV guests Paolo Bonzini
2025-07-14 11:03 ` [PULL 31/77] i386/sev: Add implementation of CGS set_guest_policy() Paolo Bonzini
2025-07-14 11:03 ` [PULL 32/77] sev: Provide sev_features flags from IGVM VMSA to KVM_SEV_INIT2 Paolo Bonzini
2025-07-14 11:03 ` [PULL 33/77] i386/cpu: Move the implementation of is_host_cpu_intel() host-cpu.c Paolo Bonzini
2025-07-14 11:03 ` [PULL 34/77] i386/cpu: Use CPUID_MODEL_ID_SZ instead of hardcoded 48 Paolo Bonzini
2025-07-14 11:03 ` [PULL 35/77] i386: Cleanup the usage of CPUID_VENDOR_INTEL_1 Paolo Bonzini
2025-07-14 11:03 ` [PULL 36/77] i386/kvm-cpu: Fix the indentation inside kvm_cpu_realizefn() Paolo Bonzini
2025-07-14 11:03 ` [PULL 37/77] i386/cpu: Unify family, model and stepping calculation for x86 CPU Paolo Bonzini
2025-07-14 11:03 ` [PULL 38/77] i386/tdx: Remove task->watch only when it's valid Paolo Bonzini
2025-07-14 11:03 ` [PULL 39/77] i386/tdx: Don't mask off CPUID_EXT_PDCM Paolo Bonzini
2025-07-14 11:03 ` [PULL 40/77] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Paolo Bonzini
2025-07-14 11:03 ` Paolo Bonzini [this message]
2025-07-14 11:03 ` [PULL 42/77] i386/cpu: Add default cache model for Intel CPUs with level < 4 Paolo Bonzini
2025-07-14 11:03 ` [PULL 43/77] i386/cpu: Present same cache model in CPUID 0x2 & 0x4 Paolo Bonzini
2025-07-14 11:03 ` [PULL 44/77] i386/cpu: Consolidate CPUID 0x4 leaf Paolo Bonzini
2025-07-14 11:03 ` [PULL 45/77] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState Paolo Bonzini
2025-07-14 11:03 ` [PULL 46/77] i386/cpu: Add x-vendor-cpuid-only-v2 option for compatibility Paolo Bonzini
2025-07-14 11:03 ` [PULL 47/77] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Paolo Bonzini
2025-07-14 11:03 ` [PULL 48/77] i386/cpu: Rename AMD_ENC_ASSOC to X86_ENC_ASSOC Paolo Bonzini
2025-07-14 11:03 ` [PULL 49/77] i386/cpu: Fix CPUID[0x80000006] for Intel CPU Paolo Bonzini
2025-07-14 11:03 ` [PULL 50/77] i386/cpu: Add legacy_intel_cache_info cache model Paolo Bonzini
2025-07-14 11:03 ` [PULL 51/77] i386/cpu: Add legacy_amd_cache_info " Paolo Bonzini
2025-07-14 11:03 ` [PULL 52/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x2 Paolo Bonzini
2025-07-14 11:03 ` [PULL 53/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x4 Paolo Bonzini
2025-07-14 11:03 ` [PULL 54/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005 Paolo Bonzini
2025-07-14 11:03 ` [PULL 55/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006 Paolo Bonzini
2025-07-14 11:03 ` [PULL 56/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D Paolo Bonzini
2025-07-14 11:03 ` [PULL 57/77] i386/cpu: Use a unified cache_info in X86CPUState Paolo Bonzini
2025-07-14 11:03 ` [PULL 58/77] i386/cpu: Introduce cache model for SierraForest Paolo Bonzini
2025-07-14 11:03 ` [PULL 59/77] i386/cpu: Introduce cache model for GraniteRapids Paolo Bonzini
2025-07-14 11:03 ` [PULL 60/77] i386/cpu: Introduce cache model for SapphireRapids Paolo Bonzini
2025-07-14 11:03 ` [PULL 61/77] i386/cpu: Introduce cache model for YongFeng Paolo Bonzini
2025-07-14 11:03 ` [PULL 62/77] i386/cpu: Add a "x-force-cpuid-0x1f" property Paolo Bonzini
2025-07-14 11:03 ` [PULL 63/77] i386/cpu: Enable 0x1f leaf for SierraForest by default Paolo Bonzini
2025-07-14 11:03 ` [PULL 64/77] " Paolo Bonzini
2025-07-14 11:03 ` [PULL 65/77] i386/cpu: Enable 0x1f leaf for GraniteRapids " Paolo Bonzini
2025-07-14 11:03 ` [PULL 66/77] i386/cpu: Enable 0x1f leaf for SapphireRapids " Paolo Bonzini
2025-07-14 11:03 ` [PULL 67/77] i386/cpu: Enable 0x1f leaf for YongFeng " Paolo Bonzini
2025-07-14 11:03 ` [PULL 68/77] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel Paolo Bonzini
2025-07-14 11:03 ` [PULL 69/77] i386/cpu: Mark CPUID 0x80000007[EBX] " Paolo Bonzini
2025-07-14 11:03 ` [PULL 70/77] i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin Paolo Bonzini
2025-07-14 11:04 ` [PULL 71/77] tests/functional: test_x86_cpu_model_versions: remove dead tests Paolo Bonzini
2025-07-14 11:04 ` [PULL 72/77] tests/vm: bump FreeBSD image to 14.3 Paolo Bonzini
2025-07-14 11:04 ` [PULL 73/77] i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid() Paolo Bonzini
2025-07-14 11:04 ` [PULL 74/77] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16] Paolo Bonzini
2025-07-14 11:04 ` [PULL 75/77] i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16] Paolo Bonzini
2025-07-14 11:04 ` [PULL 76/77] i386/cpu: Fix overflow of cache topology fields in CPUID.04H Paolo Bonzini
2025-07-14 11:04 ` [PULL 77/77] i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14] Paolo Bonzini
2025-07-15 19:50 ` [PULL 00/77] Rust, target/i386 changes for QEMU 10.1 soft freeze Stefan Hajnoczi
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