From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, gustavo.romero@linaro.org,
pierrick.bouvier@linaro.org
Subject: [PATCH v8 4/4] target/arm: Enable FEAT_MEC in -cpu max
Date: Mon, 14 Jul 2025 09:58:35 -0600 [thread overview]
Message-ID: <20250714155836.1514748-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250714155836.1514748-1-richard.henderson@linaro.org>
From: Gustavo Romero <gustavo.romero@linaro.org>
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a
first step to fully support FEAT_MEC.
The FEAT_MEC is an extension to FEAT_RME that implements multiple
Memory Encryption Contexts (MEC) so the memory in a realm can be
encrypted and accessing it from the wrong encryption context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC should work properly.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250711140828.1714666-7-gustavo.romero@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/cpu64.c | 1 +
docs/system/arm/emulation.rst | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 4eb51420ef..c54aa528c6 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1250,6 +1250,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = GET_IDREG(isar, ID_AA64MMFR3);
t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */
t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */
+ t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */
t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
SET_IDREG(isar, ID_AA64MMFR3, t);
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 1c597d8673..d207a9f266 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -89,6 +89,9 @@ the following architecture extensions:
- FEAT_LSE (Large System Extensions)
- FEAT_LSE2 (Large System Extensions v2)
- FEAT_LVA (Large Virtual Address space)
+- FEAT_MEC (Memory Encryption Contexts)
+
+ * This is a register-only implementation without encryption.
- FEAT_MixedEnd (Mixed-endian support)
- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
- FEAT_MOPS (Standardization of memory operations)
--
2.43.0
next prev parent reply other threads:[~2025-07-14 16:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 15:58 [PATCH v8 0/4] target/arm: Add FEAT_MEC to max cpu Richard Henderson
2025-07-14 15:58 ` [PATCH v8 1/4] target/arm: Implement FEAT_SCTLR2 and enable with -cpu max Richard Henderson
2025-07-14 15:58 ` [PATCH v8 2/4] target/arm: Implement FEAT_TCR2 " Richard Henderson
2025-07-14 15:58 ` [PATCH v8 3/4] target/arm: Implement FEAT_MEC registers Richard Henderson
2025-07-14 15:58 ` Richard Henderson [this message]
2025-07-14 17:09 ` [PATCH v8 0/4] target/arm: Add FEAT_MEC to max cpu Pierrick Bouvier
2025-07-14 23:31 ` Gustavo Romero
2025-07-15 1:26 ` Pierrick Bouvier
2025-07-16 3:13 ` Gustavo Romero
2025-07-16 5:56 ` Pierrick Bouvier
2025-07-16 13:02 ` Gustavo Romero
2025-07-15 21:29 ` Pierrick Bouvier
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