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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45627962384sm6015875e9.2.2025.07.14.23.19.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 14 Jul 2025 23:19:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PULL 00/17] MIPS & Co. patches for 2025-07-15 Date: Tue, 15 Jul 2025 08:19:00 +0200 Message-ID: <20250715061918.44971-1-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit 9a4e273ddec3927920c5958d2226c6b38b543336: Merge tag 'pull-tcg-20250711' of https://gitlab.com/rth7680/qemu into staging (2025-07-13 01:46:04 -0400) are available in the Git repository at: https://github.com/philmd/qemu.git tags/mips-20250715 for you to fetch changes up to 6f8ce26bb00db66e6cec632f16df3cd13e4df934: esp.c: only allow ESP commands permitted in the current asc_mode (2025-07-15 00:25:21 +0200) ---------------------------------------------------------------- MIPS patches queue - Implement CRC32[c] (Release 6) instructions - Convert Octeon LX instructions to decodetree - Restrict ITU to TCG - Fix ESP issue affecting WinNT (INACCESSIBLE_BOOT_DEVICE BSOD) - Add missing FDT dependency for some MicroBlaze machines - Remove execute bit on hppa-firmware blobs ---------------------------------------------------------------- Aleksandar Rakic (1): tests/tcg/mips: Add tests for MIPS CRC32[c] instructions Bernhard Beschow (1): hw/microblaze: Add missing FDT dependency Cole Robinson (1): roms: re-remove execute bit from hppa-firmware* Mark Cave-Ayland (7): esp.c: only raise IRQ in esp_transfer_data() for CMD_SEL, CMD_SELATN and CMD_TI commands esp.c: improve comment in esp_transfer_data() esp.h: remove separate ESPState typedef esp.c: only call dma_memory_read function if transfer length is non-zero esp.c: only call dma_memory_write function if transfer length is non-zero esp.c: add asc_mode property to indicate the current ESP mode esp.c: only allow ESP commands permitted in the current asc_mode Philippe Mathieu-Daudé (6): target/mips: Extract gen_base_index_addr() helper target/mips: Extract generic gen_lx() helper target/mips: Convert Octeon LX instructions to decodetree target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument hw/mips: Restrict ITU to TCG hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include Yongbok Kim (1): target/mips: Add support for emulation of CRC32 instructions include/hw/scsi/esp.h | 15 +- target/mips/helper.h | 2 + target/mips/tcg/translate.h | 4 + tests/tcg/mips/include/wrappers_mips64r6.h | 32 ++++ target/mips/tcg/octeon.decode | 8 + target/mips/tcg/rel6.decode | 5 + hw/intc/loongarch_extioi_kvm.c | 1 - hw/mips/cps.c | 4 +- hw/scsi/esp.c | 94 ++++++++++-- target/mips/tcg/msa_translate.c | 4 +- target/mips/tcg/octeon_translate.c | 12 ++ target/mips/tcg/op_helper.c | 26 ++++ target/mips/tcg/rel6_translate.c | 16 +- target/mips/tcg/translate.c | 102 +++++++------ target/mips/tcg/translate_addr_const.c | 4 +- .../isa/mips64r6/crc/test_mips64r6_crc32b.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32cb.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32cd.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32ch.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32cw.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32d.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32h.c | 142 ++++++++++++++++++ .../isa/mips64r6/crc/test_mips64r6_crc32w.c | 142 ++++++++++++++++++ target/mips/cpu-defs.c.inc | 10 +- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/nanomips_translate.c.inc | 7 +- hw/microblaze/Kconfig | 4 +- hw/mips/Kconfig | 2 +- hw/misc/Kconfig | 1 + hw/scsi/trace-events | 1 + pc-bios/hppa-firmware.img | Bin pc-bios/hppa-firmware64.img | Bin target/mips/meson.build | 1 + tests/tcg/mips/user/isa/mips64r6/crc/Makefile | 40 +++++ 34 files changed, 1447 insertions(+), 86 deletions(-) create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32b.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32cb.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32cd.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32ch.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32cw.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32d.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32h.c create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32w.c mode change 100755 => 100644 pc-bios/hppa-firmware.img mode change 100755 => 100644 pc-bios/hppa-firmware64.img create mode 100644 tests/tcg/mips/user/isa/mips64r6/crc/Makefile -- 2.49.0