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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Pavel Dovgalyuk" <Pavel.Dovgalyuk@ispras.ru>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Aleksandar Rikalo" <arikalo@gmail.com>
Subject: [PULL 04/17] target/mips: Convert Octeon LX instructions to decodetree
Date: Tue, 15 Jul 2025 08:19:04 +0200	[thread overview]
Message-ID: <20250715061918.44971-5-philmd@linaro.org> (raw)
In-Reply-To: <20250715061918.44971-1-philmd@linaro.org>

Use Octeon decodetree to call gen_lx() for the LX instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241111222936.59869-4-philmd@linaro.org>
---
 target/mips/tcg/octeon.decode      |  8 ++++++++
 target/mips/tcg/octeon_translate.c | 12 ++++++++++++
 target/mips/tcg/translate.c        |  4 +---
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 0c787cb498c..102a05860df 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -1,6 +1,7 @@
 # Octeon Architecture Module instruction set
 #
 # Copyright (C) 2022 Pavel Dovgalyuk
+# Copyright (C) 2024 Philippe Mathieu-Daudé
 #
 # SPDX-License-Identifier: LGPL-2.1-or-later
 #
@@ -39,3 +40,10 @@ CINS         011100 ..... ..... ..... ..... 11001 . @bitfield
 POP          011100 rs:5 00000 rd:5 00000 10110 dw:1
 SEQNE        011100 rs:5 rt:5 rd:5 00000 10101 ne:1
 SEQNEI       011100 rs:5 rt:5 imm:s10 10111 ne:1
+
+&lx          base index rd
+@lx          ...... base:5 index:5 rd:5 ...... ..... &lx
+LWX          011111 ..... ..... ..... 00000 001010 @lx
+LHX          011111 ..... ..... ..... 00100 001010 @lx
+LBUX         011111 ..... ..... ..... 00110 001010 @lx
+LDX          011111 ..... ..... ..... 01000 001010 @lx
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index d9eb43716e2..b2eca29e06c 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -174,3 +174,15 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
     }
     return true;
 }
+
+static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
+{
+    gen_lx(ctx, a->rd, a->base, a->index, mop);
+
+    return true;
+}
+
+TRANS(LBUX, trans_lx, MO_UB);
+TRANS(LHX,  trans_lx, MO_SW);
+TRANS(LWX,  trans_lx, MO_SL);
+TRANS(LDX,  trans_lx, MO_UQ);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index b9b2d8bb7e1..d91d6efe02c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -13607,9 +13607,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_LX_DSP:
-        if (!(ctx->insn_flags & INSN_OCTEON)) {
-            check_dsp(ctx);
-        }
+        check_dsp(ctx);
         op2 = MASK_LX(ctx->opcode);
         switch (op2) {
 #if defined(TARGET_MIPS64)
-- 
2.49.0



  parent reply	other threads:[~2025-07-15  6:20 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-15  6:19 [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 01/17] target/mips: Add support for emulation of CRC32 instructions Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 02/17] target/mips: Extract gen_base_index_addr() helper Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 03/17] target/mips: Extract generic gen_lx() helper Philippe Mathieu-Daudé
2025-07-15  6:19 ` Philippe Mathieu-Daudé [this message]
2025-07-15  6:19 ` [PULL 05/17] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 06/17] tests/tcg/mips: Add tests for MIPS CRC32[c] instructions Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 07/17] roms: re-remove execute bit from hppa-firmware* Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 08/17] hw/mips: Restrict ITU to TCG Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 09/17] hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 10/17] hw/microblaze: Add missing FDT dependency Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 11/17] esp.c: only raise IRQ in esp_transfer_data() for CMD_SEL, CMD_SELATN and CMD_TI commands Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 12/17] esp.c: improve comment in esp_transfer_data() Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 13/17] esp.h: remove separate ESPState typedef Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 14/17] esp.c: only call dma_memory_read function if transfer length is non-zero Philippe Mathieu-Daudé
2025-07-17 11:48   ` Philippe Mathieu-Daudé
2025-07-17 11:58     ` Peter Maydell
2025-07-17 12:37       ` Mark Cave-Ayland
2025-07-15  6:19 ` [PULL 15/17] esp.c: only call dma_memory_write " Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 16/17] esp.c: add asc_mode property to indicate the current ESP mode Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 17/17] esp.c: only allow ESP commands permitted in the current asc_mode Philippe Mathieu-Daudé
2025-07-15  6:50 ` [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-16 12:40 ` Stefan Hajnoczi

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