* [PATCH v2 1/3] Add-the-stm32f407-SoC
2025-07-21 20:11 [PATCH v2 0/3] Add STM32F4 support and USART device model fanyihao
@ 2025-07-21 20:11 ` fanyihao
2025-08-15 17:56 ` Peter Maydell
2025-07-21 20:11 ` [PATCH v2 2/3] Add the STM32F4spark Machine fanyihao
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: fanyihao @ 2025-07-21 20:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Yihao Fan
From: Yihao Fan <fanyihao@rt-thread.org>
This patch introduces a new QEMU machine type for the STM32F407 SoC featuring a Cortex-M4 core.
This will be used by the RT-Spark to create a machine.
Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
---
MAINTAINERS | 7 ++
hw/arm/Kconfig | 6 ++
hw/arm/meson.build | 1 +
hw/arm/stm32f407_soc.c | 130 +++++++++++++++++++++++++++++++++
include/hw/arm/stm32f407_soc.h | 39 ++++++++++
5 files changed, 183 insertions(+)
create mode 100644 hw/arm/stm32f407_soc.c
create mode 100644 include/hw/arm/stm32f407_soc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d1672fda8d..2744639a8b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1137,6 +1137,13 @@ F: hw/misc/stm32f4xx_exti.c
F: hw/misc/stm32_rcc.c
F: include/hw/misc/stm32_rcc.h
+STM32F407
+M: yanl1229 <yanl1229@rt-thread.org>
+M: Yihao Fan <fanyihao@rt-thread.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f407_soc.c
+
Netduino 2
M: Alistair Francis <alistair@alistair23.me>
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index f543d944c3..4b2f71e6e1 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -392,6 +392,12 @@ config STM32F405_SOC
select STM32F4XX_SYSCFG
select STM32F4XX_EXTI
+config STM32F407_SOC
+ bool
+ select ARM_V7M
+ select STM32F4XX_SYSCFG
+ select STM32F4XX_EXTI
+
config B_L475E_IOT01A
bool
default y
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index d90be8f4c9..31621060ba 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -32,6 +32,7 @@ arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2
arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
+arm_common_ss.add(when: 'CONFIG_STM32F407_SOC', if_true: files('stm32f407_soc.c'))
arm_common_ss.add(when: 'CONFIG_B_L475E_IOT01A', if_true: files('b-l475e-iot01a.c'))
arm_common_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_soc.c'))
arm_common_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
diff --git a/hw/arm/stm32f407_soc.c b/hw/arm/stm32f407_soc.c
new file mode 100644
index 0000000000..0a91d4bb10
--- /dev/null
+++ b/hw/arm/stm32f407_soc.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "system/address-spaces.h"
+#include "system/system.h"
+#include "hw/arm/stm32f407_soc.h"
+#include "hw/qdev-clock.h"
+#include "hw/sd/sd.h"
+#include "hw/boards.h"
+#include "qom/object.h"
+#include "hw/block/flash.h"
+#include "hw/misc/unimp.h"
+
+
+static const uint32_t syscfg_addr = 0x40013800;
+static const uint32_t exti_addr = 0x40013C00;
+static const int syscfg_irq = 71;
+static const int exti_irq[] = {
+ 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
+ 40, 40, 40, 40, 40
+};
+
+
+static void stm32f407_soc_initfn(Object *obj)
+{
+ int i;
+
+ STM32F407State *s = STM32F407_SOC(obj);
+
+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+ object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
+ object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
+}
+
+static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ STM32F407State *s = STM32F407_SOC(dev_soc);
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
+ DriveInfo *dinfo;
+ int i, j;
+
+ MemoryRegion *system_memory = get_system_memory();
+
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk clock must not be wired up by the board code");
+ return;
+ }
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC RCC and its ability to
+ * change the sysclk frequency and define different sysclk sources.
+ */
+
+ /* The refclk always runs at frequency HCLK / 8 */
+ clock_set_mul_div(s->refclk, 8, 1);
+ clock_set_source(s->refclk, s->sysclk);
+
+
+ armv7m = DEVICE(&s->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 98);
+ qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
+ object_property_set_link(OBJECT(&s->armv7m), "memory",
+ OBJECT(system_memory), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
+ return;
+ }
+ /* System configuration controller */
+ dev = DEVICE(&s->syscfg);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, syscfg_addr);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, syscfg_irq));
+
+ /* EXTI device */
+ dev = DEVICE(&s->exti);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, exti_addr);
+ for (i = 0; i < 16; i) {
+ sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
+ }
+ for (i = 0; i < 16; i) {
+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
+ }
+
+}
+
+static void stm32f407_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = stm32f407_soc_realize;
+}
+
+static const TypeInfo stm32f407_soc_info = {
+ .name = TYPE_STM32F407_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F407State),
+ .instance_init = stm32f407_soc_initfn,
+ .class_init = stm32f407_soc_class_init,
+};
+
+static void stm32f407_soc_types(void)
+{
+ type_register_static(&stm32f407_soc_info);
+}
+
+type_init(stm32f407_soc_types)
diff --git a/include/hw/arm/stm32f407_soc.h b/include/hw/arm/stm32f407_soc.h
new file mode 100644
index 0000000000..19191dc44e
--- /dev/null
+++ b/include/hw/arm/stm32f407_soc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef STM32F407_SOC_H
+#define STM32F407_SOC_H
+
+#include "hw/or-irq.h"
+#include "hw/arm/armv7m.h"
+#include "hw/misc/stm32f4xx_syscfg.h"
+#include "hw/misc/stm32f4xx_exti.h"
+
+#include "qom/object.h"
+
+#define TYPE_STM32F407_SOC "stm32f407-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F407State, STM32F407_SOC)
+
+#define SYSCFG_BASE_ADDRESS 0x40013800
+#define SYSCFG_IRQ 71
+#define EXIT_BASE_ADDRESS 0x40013C00
+#define FLASH_BASE_ADDRESS 0x8000000
+#define FLASH_SIZE 0x100000
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (192 * 1024)
+
+
+struct STM32F407State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ char *kernel_filename;
+ ARMv7MState armv7m;
+
+ STM32F4xxSyscfgState syscfg;
+ STM32F4xxExtiState exti;
+
+ Clock *sysclk;
+ Clock *refclk;
+};
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 1/3] Add-the-stm32f407-SoC
2025-07-21 20:11 ` [PATCH v2 1/3] Add-the-stm32f407-SoC fanyihao
@ 2025-08-15 17:56 ` Peter Maydell
2025-08-21 14:02 ` 范艺豪
0 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2025-08-15 17:56 UTC (permalink / raw)
To: fanyihao; +Cc: qemu-devel, Alistair Francis
On Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch introduces a new QEMU machine type for the STM32F407 SoC featuring a Cortex-M4 core.
> This will be used by the RT-Spark to create a machine.
The Subject line of this patch seems to have hyphens
instead of spaces. A "hw/arm:" prefix would also be helpful.
> diff --git a/hw/arm/stm32f407_soc.c b/hw/arm/stm32f407_soc.c
> new file mode 100644
> index 0000000000..0a91d4bb10
> --- /dev/null
> +++ b/hw/arm/stm32f407_soc.c
> @@ -0,0 +1,130 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
This seems very similar to the existing stm32f05_soc.c.
How different are these two SoCs? Would it make sense
to share code?
I've cc'd Alistair as the maintainer of the stm32f05.
thanks
-- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/3] Add-the-stm32f407-SoC
2025-08-15 17:56 ` Peter Maydell
@ 2025-08-21 14:02 ` 范艺豪
0 siblings, 0 replies; 15+ messages in thread
From: 范艺豪 @ 2025-08-21 14:02 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 1441 bytes --]
Hi,
Thanks for the comment.
The STM32F407 is similar to the STM32F405. The main differences are in peripherals (the F407 integrates Ethernet MAC and a camera interface, which the F405 lacks).
I’ll review the common parts and see what code can be shared in revision V3.
Best Wishes,
--Yihao Fan
范艺豪
fanyihao@rt-thread.org
Original:
From：Peter Maydell <peter.maydell@linaro.org>Date：2025-08-16 01:56:02(中国 (GMT+08:00))To：fanyihao<fanyihao@rt-thread.org>Cc：qemu-devel<qemu-devel@nongnu.org> , Alistair Francis <alistair@alistair23.me>Subject：Re: [PATCH v2 1/3] Add-the-stm32f407-SoCOn Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch introduces a new QEMU machine type for the STM32F407 SoC featuring a Cortex-M4 core.
> This will be used by the RT-Spark to create a machine.
The Subject line of this patch seems to have hyphens
instead of spaces. A "hw/arm:" prefix would also be helpful.
> diff --git a/hw/arm/stm32f407_soc.c b/hw/arm/stm32f407_soc.c
> new file mode 100644
> index 0000000000..0a91d4bb10
> --- /dev/null
> +++ b/hw/arm/stm32f407_soc.c
> @@ -0,0 +1,130 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
This seems very similar to the existing stm32f05_soc.c.
How different are these two SoCs? Would it make sense
to share code?
I've cc'd Alistair as the maintainer of the stm32f05.
thanks
-- PMM
[-- Attachment #2: Type: text/html, Size: 4465 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/3] Add the STM32F4spark Machine
2025-07-21 20:11 [PATCH v2 0/3] Add STM32F4 support and USART device model fanyihao
2025-07-21 20:11 ` [PATCH v2 1/3] Add-the-stm32f407-SoC fanyihao
@ 2025-07-21 20:11 ` fanyihao
2025-08-15 17:52 ` Peter Maydell
2025-07-21 20:11 ` [PATCH v2 3/3] Add STM32F4xx USART device model fanyihao
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: fanyihao @ 2025-07-21 20:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Yihao Fan
From: Yihao Fan <fanyihao@rt-thread.org>
Add the STM32F4spark machine model using the STM32F407 SoC.
Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
---
MAINTAINERS | 7 +++++++
hw/arm/Kconfig | 6 ++++++
hw/arm/meson.build | 1 +
hw/arm/stm32f4spark.c | 48 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 62 insertions(+)
create mode 100644 hw/arm/stm32f4spark.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 2744639a8b..0dc7c7bf60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1030,6 +1030,13 @@ S: Maintained
F: hw/arm/stm32vldiscovery.c
F: docs/system/arm/stm32.rst
+STM32F4SPARK
+M: yanl1229 <yanl1229@rt-thread.org>
+M: Yihao Fan <fanyihao@rt-thread.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f4spark.c
+
Versatile Express
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4b2f71e6e1..3706a65286 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -234,6 +234,12 @@ config STM32VLDISCOVERY
depends on TCG && ARM
select STM32F100_SOC
+config STM32F4SPARK
+ bool
+ default y
+ depends on TCG && ARM
+ select STM32F407_SOC
+
config STRONGARM
bool
select PXA2XX_TIMER
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 31621060ba..ec63ed7373 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -17,6 +17,7 @@ arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
+arm_common_ss.add(when: 'CONFIG_STM32F4SPARK', if_true: files('stm32f4spark.c'))
arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
arm_common_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
diff --git a/hw/arm/stm32f4spark.c b/hw/arm/stm32f4spark.c
new file mode 100644
index 0000000000..e1d656a3f9
--- /dev/null
+++ b/hw/arm/stm32f4spark.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f407_soc.h"
+#include "hw/arm/boot.h"
+
+/* stm32f4spark implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (72MHz) */
+#define SYSCLK_FRQ 72000000ULL
+
+
+static void stm32f4spark_init(MachineState *machine)
+{
+ DeviceState *dev;
+ Clock *sysclk;
+
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ dev = qdev_new(TYPE_STM32F407_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ 0, FLASH_SIZE);
+}
+
+static void stm32f4spark_machine_init(MachineClass *mc)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"),
+ NULL
+ };
+
+ mc->desc = "ST RT-spark (Cortex-M4)";
+ mc->init = stm32f4spark_init;
+ mc->valid_cpu_types = valid_cpu_types;
+}
+
+DEFINE_MACHINE("rt-spark", stm32f4spark_machine_init)
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 2/3] Add the STM32F4spark Machine
2025-07-21 20:11 ` [PATCH v2 2/3] Add the STM32F4spark Machine fanyihao
@ 2025-08-15 17:52 ` Peter Maydell
2025-08-21 14:04 ` 范艺豪
0 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2025-08-15 17:52 UTC (permalink / raw)
To: fanyihao; +Cc: qemu-devel
On Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> Add the STM32F4spark machine model using the STM32F407 SoC.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
> ---
> MAINTAINERS | 7 +++++++
> hw/arm/Kconfig | 6 ++++++
> hw/arm/meson.build | 1 +
> hw/arm/stm32f4spark.c | 48 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 62 insertions(+)
> create mode 100644 hw/arm/stm32f4spark.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2744639a8b..0dc7c7bf60 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1030,6 +1030,13 @@ S: Maintained
> F: hw/arm/stm32vldiscovery.c
> F: docs/system/arm/stm32.rst
>
> +STM32F4SPARK
> +M: yanl1229 <yanl1229@rt-thread.org>
> +M: Yihao Fan <fanyihao@rt-thread.org>
> +L: qemu-arm@nongnu.org
> +S: Maintained
> +F: hw/arm/stm32f4spark.c
> +
> Versatile Express
> M: Peter Maydell <peter.maydell@linaro.org>
> L: qemu-arm@nongnu.org
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 4b2f71e6e1..3706a65286 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -234,6 +234,12 @@ config STM32VLDISCOVERY
> depends on TCG && ARM
> select STM32F100_SOC
>
> +config STM32F4SPARK
> + bool
> + default y
> + depends on TCG && ARM
> + select STM32F407_SOC
> +
> config STRONGARM
> bool
> select PXA2XX_TIMER
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 31621060ba..ec63ed7373 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -17,6 +17,7 @@ arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
> arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
> arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
> arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
> +arm_common_ss.add(when: 'CONFIG_STM32F4SPARK', if_true: files('stm32f4spark.c'))
> arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
> arm_common_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
>
> diff --git a/hw/arm/stm32f4spark.c b/hw/arm/stm32f4spark.c
> new file mode 100644
> index 0000000000..e1d656a3f9
> --- /dev/null
> +++ b/hw/arm/stm32f4spark.c
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
Generally files should have something more than just the SPDX
tag in their opening comment. Usually that is a statement
of what the file contains. This is also a good place to put
a URL to the datasheet/reference manual/etc for the hardware
being modelled.
Otherwise this patch looks OK.
-- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 2/3] Add the STM32F4spark Machine
2025-08-15 17:52 ` Peter Maydell
@ 2025-08-21 14:04 ` 范艺豪
0 siblings, 0 replies; 15+ messages in thread
From: 范艺豪 @ 2025-08-21 14:04 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3044 bytes --]
Hi,
Thanks, I’ll add the description and datasheet link in the next revision.
Best wishes,
-- Yihao Fan
范艺豪
fanyihao@rt-thread.org
Original:
From：Peter Maydell <peter.maydell@linaro.org>Date：2025-08-16 01:52:19(中国 (GMT+08:00))To：fanyihao<fanyihao@rt-thread.org>Cc：qemu-devel<qemu-devel@nongnu.org>Subject：Re: [PATCH v2 2/3] Add the STM32F4spark MachineOn Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> Add the STM32F4spark machine model using the STM32F407 SoC.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
> ---
> MAINTAINERS | 7 +++++++
> hw/arm/Kconfig | 6 ++++++
> hw/arm/meson.build | 1 +
> hw/arm/stm32f4spark.c | 48 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 62 insertions(+)
> create mode 100644 hw/arm/stm32f4spark.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2744639a8b..0dc7c7bf60 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1030,6 +1030,13 @@ S: Maintained
> F: hw/arm/stm32vldiscovery.c
> F: docs/system/arm/stm32.rst
>
> +STM32F4SPARK
> +M: yanl1229 <yanl1229@rt-thread.org>
> +M: Yihao Fan <fanyihao@rt-thread.org>
> +L: qemu-arm@nongnu.org
> +S: Maintained
> +F: hw/arm/stm32f4spark.c
> +
> Versatile Express
> M: Peter Maydell <peter.maydell@linaro.org>
> L: qemu-arm@nongnu.org
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 4b2f71e6e1..3706a65286 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -234,6 +234,12 @@ config STM32VLDISCOVERY
> depends on TCG && ARM
> select STM32F100_SOC
>
> +config STM32F4SPARK
> + bool
> + default y
> + depends on TCG && ARM
> + select STM32F407_SOC
> +
> config STRONGARM
> bool
> select PXA2XX_TIMER
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 31621060ba..ec63ed7373 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -17,6 +17,7 @@ arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
> arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
> arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
> arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
> +arm_common_ss.add(when: 'CONFIG_STM32F4SPARK', if_true: files('stm32f4spark.c'))
> arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
> arm_common_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
>
> diff --git a/hw/arm/stm32f4spark.c b/hw/arm/stm32f4spark.c
> new file mode 100644
> index 0000000000..e1d656a3f9
> --- /dev/null
> +++ b/hw/arm/stm32f4spark.c
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
Generally files should have something more than just the SPDX
tag in their opening comment. Usually that is a statement
of what the file contains. This is also a good place to put
a URL to the datasheet/reference manual/etc for the hardware
being modelled.
Otherwise this patch looks OK.
-- PMM
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/3] Add STM32F4xx USART device model
2025-07-21 20:11 [PATCH v2 0/3] Add STM32F4 support and USART device model fanyihao
2025-07-21 20:11 ` [PATCH v2 1/3] Add-the-stm32f407-SoC fanyihao
2025-07-21 20:11 ` [PATCH v2 2/3] Add the STM32F4spark Machine fanyihao
@ 2025-07-21 20:11 ` fanyihao
2025-08-15 17:46 ` Peter Maydell
2025-08-02 6:12 ` Re:[PATCH v2 0/3] Add STM32F4 support and " 范艺豪
2025-08-15 17:49 ` Peter Maydell
4 siblings, 1 reply; 15+ messages in thread
From: fanyihao @ 2025-07-21 20:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Yihao Fan
From: Yihao Fan <fanyihao@rt-thread.org>
This patch adds support for the STM32F407 USART controllers device model.
Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
---
MAINTAINERS | 2 +
hw/arm/Kconfig | 1 +
hw/arm/stm32f407_soc.c | 25 +++
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
include/hw/arm/stm32f407_soc.h | 8 +
include/hw/char/stm32f4xx_usart.h | 60 ++++++++
8 files changed, 335 insertions(+)
create mode 100644 hw/char/stm32f4xx_usart.c
create mode 100644 include/hw/char/stm32f4xx_usart.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 0dc7c7bf60..2054aba27e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1150,6 +1150,8 @@ M: Yihao Fan <fanyihao@rt-thread.org>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/stm32f407_soc.c
+F: hw/char/stm32f4xx_usart.c
+F: include/hw/char/stm32f4xx_usart.h
Netduino 2
M: Alistair Francis <alistair@alistair23.me>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3706a65286..c6a4919266 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -403,6 +403,7 @@ config STM32F407_SOC
select ARM_V7M
select STM32F4XX_SYSCFG
select STM32F4XX_EXTI
+ select STM32F4XX_USART
config B_L475E_IOT01A
bool
diff --git a/hw/arm/stm32f407_soc.c b/hw/arm/stm32f407_soc.c
index 0a91d4bb10..8a929674af 100644
--- a/hw/arm/stm32f407_soc.c
+++ b/hw/arm/stm32f407_soc.c
@@ -20,6 +20,13 @@ static const int exti_irq[] = {
40, 40, 40, 40, 40
};
+static const uint32_t usart_addr[STM_NUM_USARTS] = {
+ STM32F407_USART1, STM32F407_USART2, STM32F407_USART3,
+ STM32F407_USART6
+};
+static const int usart_irq[STM_NUM_USARTS] = {
+ 37, 38, 39, 71
+};
static void stm32f407_soc_initfn(Object *obj)
{
@@ -32,6 +40,12 @@ static void stm32f407_soc_initfn(Object *obj)
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
+ for (i = 0; i < STM_NUM_USARTS; i++) {
+ object_initialize_child(obj, "usart[*]", &s->usart[i],
+ TYPE_STM32F4XX_USART);
+ }
+
+
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
@@ -105,6 +117,18 @@ static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
}
+ /* USART controllers */
+ for (i = 0; i < STM_NUM_USARTS; i) {
+ dev = DEVICE(&(s->usart[i]));
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+ }
+
}
static void stm32f407_soc_class_init(ObjectClass *klass, void *data)
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 9d517f3e28..25a0483fb3 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -51,6 +51,9 @@ config VIRTIO_SERIAL
config STM32F2XX_USART
bool
+config STM32F4XX_USART
+ bool
+
config STM32L4X5_USART
bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 4e439da8b9..3372e77bbc 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -32,6 +32,7 @@ system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
system_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
system_ss.add(when: 'CONFIG_SH_SCI', if_true: files('sh_serial.c'))
system_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
+system_ss.add(when: 'CONFIG_STM32F4XX_USART', if_true: files('stm32f4xx_usart.c'))
system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: files('stm32l4x5_usart.c'))
system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
diff --git a/hw/char/stm32f4xx_usart.c b/hw/char/stm32f4xx_usart.c
new file mode 100644
index 0000000000..c3d2690275
--- /dev/null
+++ b/hw/char/stm32f4xx_usart.c
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include "qemu/osdep.h"
+#include "hw/char/stm32f4xx_usart.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/module.h"
+
+#ifndef STM_USART_ERR_DEBUG
+#define STM_USART_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_USART_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0)
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static int stm32f4xx_usart_can_receive(void *opaque)
+{
+ STM32F4XXUsartState *s = opaque;
+
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void stm32f4xx_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ STM32F4XXUsartState *s = opaque;
+
+ s->usart_dr = *buf;
+
+ if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
+ /* USART not enabled - drop the chars */
+ DB_PRINT("Dropping the chars\n");
+ return;
+ }
+
+ s->usart_sr |= USART_SR_RXNE;
+
+ if (s->usart_cr1 & USART_CR1_RXNEIE) {
+ qemu_set_irq(s->irq, 1);
+ }
+
+ DB_PRINT("Receiving: %c\n", s->usart_dr);
+}
+
+static void stm32f4xx_usart_reset(DeviceState *dev)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(dev);
+
+ s->usart_sr = USART_SR_RESET;
+ s->usart_dr = 0x00000000;
+ s->usart_brr = 0x00000000;
+ s->usart_cr1 = 0x00000000;
+ s->usart_cr2 = 0x00000000;
+ s->usart_cr3 = 0x00000000;
+ s->usart_gtpr = 0x00000000;
+
+ qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t stm32f4xx_usart_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F4XXUsartState *s = opaque;
+ uint64_t retvalue;
+
+ DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
+
+ switch (addr) {
+ case USART_SR:
+ retvalue = s->usart_sr;
+ qemu_chr_fe_accept_input(&s->chr);
+ return retvalue;
+ case USART_DR:
+ DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
+ s->usart_sr |= USART_SR_TXE;
+ s->usart_sr &= ~USART_SR_RXNE;
+ qemu_chr_fe_accept_input(&s->chr);
+ qemu_set_irq(s->irq, 0);
+ if (s->usart_cr1 & USART_CR1_M) {
+ return s->usart_dr & 0x1FF;
+ } else {
+ return s->usart_dr & 0xFF;
+ }
+ case USART_BRR:
+ return s->usart_brr;
+ case USART_CR1:
+ return s->usart_cr1;
+ case USART_CR2:
+ return s->usart_cr2;
+ case USART_CR3:
+ return s->usart_cr3;
+ case USART_GTPR:
+ return s->usart_gtpr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void stm32f4xx_usart_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F4XXUsartState *s = opaque;
+ uint32_t value = val64;
+ unsigned char ch;
+
+ DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
+
+ switch (addr) {
+ case USART_SR:
+ if (value <= 0x3FF) {
+ s->usart_sr |= value;
+ } else {
+ s->usart_sr &= value;
+ }
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ qemu_set_irq(s->irq, 0);
+ }
+ return;
+ case USART_DR:
+ if (s->usart_cr1 & USART_CR1_M) {
+ ch = value & 0x1FF;
+ } else {
+ ch = value & 0xFF;
+ }
+ if (!(s->usart_cr1 & USART_CR1_TE)) {
+ return;
+ }
+ if ((s->usart_sr & USART_SR_TC)) {
+ s->usart_sr &= ~USART_SR_TC;
+ }
+ ch = value;
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
+ s->usart_sr |= USART_SR_TXE;
+ if (s->usart_cr1 & USART_CR1_TXEIE) {
+ qemu_set_irq(s->irq, 0);
+ }
+ s->usart_sr |= USART_SR_TC;
+ if (s->usart_cr1 & USART_CR1_TCIE) {
+ qemu_set_irq(s->irq, 0);
+ }
+ break;
+ case USART_BRR:
+ s->usart_brr |= value & 0xFFFF;
+ break;
+ case USART_CR1:
+ if (!(s->usart_cr1 & USART_CR1_TE) && (value & USART_CR1_TE)) {
+ s->usart_dr = 0xFF;
+ }
+ s->usart_cr1 |= value & 0xFFFF;
+ if (s->usart_cr1 & USART_CR1_RXNEIE &&
+ s->usart_sr & USART_SR_RXNE) {
+ qemu_set_irq(s->irq, 0);
+ }
+ break;
+ case USART_CR2:
+ s->usart_cr2 |= value & 0xFFFF;
+ break;
+ case USART_CR3:
+ s->usart_cr3 |= value;
+ break;
+ case USART_GTPR:
+ s->usart_gtpr |= value & 0xFFFF;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ break;
+ }
+}
+
+static const MemoryRegionOps stm32f4xx_usart_ops = {
+ .read = stm32f4xx_usart_read,
+ .write = stm32f4xx_usart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static Property stm32f4xx_usart_properties[] = {
+ DEFINE_PROP_CHR("chardev", STM32F4XXUsartState, chr),
+};
+
+static void stm32f4xx_usart_init(Object *obj)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_usart_ops, s,
+ TYPE_STM32F4XX_USART, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f4xx_usart_realize(DeviceState *dev, Error **errp)
+{
+ STM32F4XXUsartState *s = STM32F4XX_USART(dev);
+
+ qemu_chr_fe_set_handlers(&s->chr, stm32f4xx_usart_can_receive,
+ stm32f4xx_usart_receive, NULL, NULL,
+ s, NULL, true);
+}
+
+static void stm32f4xx_usart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ device_class_set_legacy_reset(dc, stm32f4xx_usart_reset);
+ device_class_set_props(dc, stm32f4xx_usart_properties);
+ dc->realize = stm32f4xx_usart_realize;
+}
+
+static const TypeInfo stm32f4xx_usart_info = {
+ .name = TYPE_STM32F4XX_USART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F4XXUsartState),
+ .instance_init = stm32f4xx_usart_init,
+ .class_init = stm32f4xx_usart_class_init,
+};
+
+static void stm32f4xx_usart_register_types(void)
+{
+ type_register_static(&stm32f4xx_usart_info);
+}
+
+type_init(stm32f4xx_usart_register_types)
diff --git a/include/hw/arm/stm32f407_soc.h b/include/hw/arm/stm32f407_soc.h
index 19191dc44e..6599e8aa48 100644
--- a/include/hw/arm/stm32f407_soc.h
+++ b/include/hw/arm/stm32f407_soc.h
@@ -6,6 +6,7 @@
#include "hw/arm/armv7m.h"
#include "hw/misc/stm32f4xx_syscfg.h"
#include "hw/misc/stm32f4xx_exti.h"
+#include "hw/char/stm32f4xx_usart.h"
#include "qom/object.h"
@@ -20,6 +21,12 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F407State, STM32F407_SOC)
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (192 * 1024)
+#define STM_NUM_USARTS 4
+#define STM32F407_USART1 0x40011000
+#define STM32F407_USART2 0x40004400
+#define STM32F407_USART3 0x40004800
+#define STM32F407_USART6 0x40011400
+
struct STM32F407State {
/*< private >*/
@@ -31,6 +38,7 @@ struct STM32F407State {
STM32F4xxSyscfgState syscfg;
STM32F4xxExtiState exti;
+ STM32F4XXUsartState usart[STM_NUM_USARTS];
Clock *sysclk;
Clock *refclk;
diff --git a/include/hw/char/stm32f4xx_usart.h b/include/hw/char/stm32f4xx_usart.h
new file mode 100644
index 0000000000..611906bd83
--- /dev/null
+++ b/include/hw/char/stm32f4xx_usart.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef HW_STM32F4XX_USART_H
+#define HW_STM32F4XX_USART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define USART_SR 0x00
+#define USART_DR 0x04
+#define USART_BRR 0x08
+#define USART_CR1 0x0C
+#define USART_CR2 0x10
+#define USART_CR3 0x14
+#define USART_GTPR 0x18
+
+#define USART_SR_RESET 0x00C0
+
+#define USART_SR_TXE (1 << 7)
+#define USART_SR_TC (1 << 6)
+#define USART_SR_RXNE (1 << 5)
+
+#define USART_CR1_UE (1 << 13)
+#define USART_CR1_RXNEIE (1 << 5)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_RE (1 << 2)
+#define USART_CR1_M (1 << 12)
+#define USART_CR1_TXEIE (1 << 7)
+#define USART_CR1_TCIE (1 << 6)
+
+#define USART_CR2_CLKEN (1 << 11)
+#define USART_CR2_LINEN (1 << 14)
+
+#define USART_CR3_SCEN (1 << 5)
+#define USART_CR3_HDSEL (1 << 3)
+#define USART_CR3_IREN (1 << 1)
+
+#define TYPE_STM32F4XX_USART "stm32f4xx-usart"
+#define STM32F4XX_USART(obj) \
+ OBJECT_CHECK(STM32F4XXUsartState, (obj), TYPE_STM32F4XX_USART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t usart_sr;
+ uint32_t usart_dr;
+ uint32_t usart_brr;
+ uint32_t usart_cr1;
+ uint32_t usart_cr2;
+ uint32_t usart_cr3;
+ uint32_t usart_gtpr;
+
+ CharBackend chr;
+ qemu_irq irq;
+} STM32F4XXUsartState;
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 3/3] Add STM32F4xx USART device model
2025-07-21 20:11 ` [PATCH v2 3/3] Add STM32F4xx USART device model fanyihao
@ 2025-08-15 17:46 ` Peter Maydell
2025-08-21 14:16 ` 范艺豪
0 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2025-08-15 17:46 UTC (permalink / raw)
To: fanyihao; +Cc: qemu-devel
On Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch adds support for the STM32F407 USART controllers device model.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
> ---
> MAINTAINERS | 2 +
> hw/arm/Kconfig | 1 +
> hw/arm/stm32f407_soc.c | 25 +++
> hw/char/Kconfig | 3 +
> hw/char/meson.build | 1 +
> hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
> include/hw/arm/stm32f407_soc.h | 8 +
> include/hw/char/stm32f4xx_usart.h | 60 ++++++++
We generally prefer two separate patches for this:
(1) implementation of the new device
(2) add the new device to the SoC
> --- /dev/null
> +++ b/hw/char/stm32f4xx_usart.c
> @@ -0,0 +1,236 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#include "qemu/osdep.h"
> +#include "hw/char/stm32f4xx_usart.h"
> +#include "qemu/log.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/qdev-properties-system.h"
> +#include "qemu/module.h"
This looks very similar to the existing stm32f2xx USART.
How different are these two devices? Could we share
code by having them be two child classes which adjust
what features the device exposes?
thanks
- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/3] Add STM32F4xx USART device model
2025-08-15 17:46 ` Peter Maydell
@ 2025-08-21 14:16 ` 范艺豪
0 siblings, 0 replies; 15+ messages in thread
From: 范艺豪 @ 2025-08-21 14:16 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1902 bytes --]
Hi,
The F4xx USART is largely similar to the F2xx. The implementation can mostly be shared,
with F4-specific features added separately, allowing a common base while keeping differences isolated.
I’ll consider sharing a common base in the next revision.
Best wishes,
-- Yihao Fan
范艺豪
fanyihao@rt-thread.org
Original:
From：Peter Maydell <peter.maydell@linaro.org>Date：2025-08-16 01:46:06(中国 (GMT+08:00))To：fanyihao<fanyihao@rt-thread.org>Cc：qemu-devel<qemu-devel@nongnu.org>Subject：Re: [PATCH v2 3/3] Add STM32F4xx USART device modelOn Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch adds support for the STM32F407 USART controllers device model.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
> ---
> MAINTAINERS | 2 +
> hw/arm/Kconfig | 1 +
> hw/arm/stm32f407_soc.c | 25 +++
> hw/char/Kconfig | 3 +
> hw/char/meson.build | 1 +
> hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
> include/hw/arm/stm32f407_soc.h | 8 +
> include/hw/char/stm32f4xx_usart.h | 60 ++++++++
We generally prefer two separate patches for this:
(1) implementation of the new device
(2) add the new device to the SoC
> --- /dev/null
> +++ b/hw/char/stm32f4xx_usart.c
> @@ -0,0 +1,236 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#include "qemu/osdep.h"
> +#include "hw/char/stm32f4xx_usart.h"
> +#include "qemu/log.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/qdev-properties-system.h"
> +#include "qemu/module.h"
This looks very similar to the existing stm32f2xx USART.
How different are these two devices? Could we share
code by having them be two child classes which adjust
what features the device exposes?
thanks
- PMM
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re:[PATCH v2 0/3] Add STM32F4 support and USART device model
2025-07-21 20:11 [PATCH v2 0/3] Add STM32F4 support and USART device model fanyihao
` (2 preceding siblings ...)
2025-07-21 20:11 ` [PATCH v2 3/3] Add STM32F4xx USART device model fanyihao
@ 2025-08-02 6:12 ` 范艺豪
2025-08-02 11:17 ` [PATCH " Peter Maydell
2025-08-15 17:49 ` Peter Maydell
4 siblings, 1 reply; 15+ messages in thread
From: 范艺豪 @ 2025-08-02 6:12 UTC (permalink / raw)
To: Yihao Fan, qemu-devel; +Cc: peter.maydell
[-- Attachment #1: Type: text/plain, Size: 2130 bytes --]
Hi,
Just a gentle ping on this patch series:
[PATCH v2 0/3] Add STM32F4 support and USART device model
https://patchew.org/QEMU/20250721201134.13270-1-fanyihao@rt-thread.org/
This patch adds support for the STM32F407 SoC, a new STM32F4spark board,
and a USART device model. Feedback would be greatly appreciated.
This patch will be applied in the /hw/arm directory.
Let me know if any changes are needed or if I should rebase it on a newer tree.
Best regards,
Yihao Fan
fanyihao@rt-thread.org
Original:
From：Yihao Fan <fanyihao@rt-thread.org>Date：2025-07-22 04:11:31(中国 (GMT+08:00))To：qemu-devel<qemu-devel@nongnu.org>Cc：Peter Maydell <peter.maydell@linaro.org> , Yihao Fan <fanyihao@rt-thread.org>Subject：[PATCH v2 0/3] Add STM32F4 support and USART device modelFrom: Yihao Fan <fanyihao@rt-thread.org>
This patch series introduces basic support for the STM32F407 SoC and
a new STM32F4spark machine in QEMU, along with a USART device model.
This series includes:
- A new SoC model (STM32F407) with initial integration.
- A board model called STM32F4spark to instantiate and test the SoC.
- A USART device implementation for STM32F4xx family.
Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
Yihao Fan (3):
Add-the-stm32f407-SoC
Add the STM32F4spark Machine
Add STM32F4xx USART device model
MAINTAINERS | 16 ++
hw/arm/Kconfig | 13 ++
hw/arm/meson.build | 2 +
hw/arm/stm32f407_soc.c | 154 +++++++++++++++++++
hw/arm/stm32f4spark.c | 48 ++++++
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
include/hw/arm/stm32f407_soc.h | 47 ++++++
include/hw/char/stm32f4xx_usart.h | 60 ++++++++
10 files changed, 580 insertions(+)
create mode 100644 hw/arm/stm32f407_soc.c
create mode 100644 hw/arm/stm32f4spark.c
create mode 100644 hw/char/stm32f4xx_usart.c
create mode 100644 include/hw/arm/stm32f407_soc.h
create mode 100644 include/hw/char/stm32f4xx_usart.h
--
2.43.0
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 0/3] Add STM32F4 support and USART device model
2025-08-02 6:12 ` Re:[PATCH v2 0/3] Add STM32F4 support and " 范艺豪
@ 2025-08-02 11:17 ` Peter Maydell
2025-08-04 15:31 ` fanyihao
0 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2025-08-02 11:17 UTC (permalink / raw)
To: 范艺豪; +Cc: qemu-devel
On Sat, 2 Aug 2025 at 07:12, 范艺豪 <fanyihao@rt-thread.org> wrote:
>
> Hi,
> Just a gentle ping on this patch series:
> [PATCH v2 0/3] Add STM32F4 support and USART device model
> https://patchew.org/QEMU/20250721201134.13270-1-fanyihao@rt-thread.org/
>
> This patch adds support for the STM32F407 SoC, a new STM32F4spark board,
> and a USART device model. Feedback would be greatly appreciated
Hi; thanks for the ping. This series is on my list to review,
but right now we are in the freeze period for the 10.1
release, so I've been concentrating on bug fix patches which are
going into the release. It may be a little while before I
can get to it. (Other people are of course welcome to review
it instead!)
thanks
-- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re:Re: [PATCH v2 0/3] Add STM32F4 support and USART device model
2025-08-02 11:17 ` [PATCH " Peter Maydell
@ 2025-08-04 15:31 ` fanyihao
0 siblings, 0 replies; 15+ messages in thread
From: fanyihao @ 2025-08-04 15:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Hi,
Thanks for the info. No problem at all. Happy to wait.
Best wishes,
— Fanyihao
在 2025-08-02 19:17:11，Peter Maydell <peter.maydell@linaro.org> 写道：
On Sat, 2 Aug 2025 at 07:12, 范艺豪 <fanyihao@rt-thread.org> wrote:
>
> Hi,
> Just a gentle ping on this patch series:
> [PATCH v2 0/3] Add STM32F4 support and USART device model
> https://patchew.org/QEMU/20250721201134.13270-1-fanyihao@rt-thread.org/
>
> This patch adds support for the STM32F407 SoC, a new STM32F4spark board,
> and a USART device model. Feedback would be greatly appreciated
Hi; thanks for the ping. This series is on my list to review,
but right now we are in the freeze period for the 10.1
release, so I've been concentrating on bug fix patches which are
going into the release. It may be a little while before I
can get to it. (Other people are of course welcome to review
it instead!)
thanks
-- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 0/3] Add STM32F4 support and USART device model
2025-07-21 20:11 [PATCH v2 0/3] Add STM32F4 support and USART device model fanyihao
` (3 preceding siblings ...)
2025-08-02 6:12 ` Re:[PATCH v2 0/3] Add STM32F4 support and " 范艺豪
@ 2025-08-15 17:49 ` Peter Maydell
2025-08-21 13:45 ` 范艺豪
4 siblings, 1 reply; 15+ messages in thread
From: Peter Maydell @ 2025-08-15 17:49 UTC (permalink / raw)
To: fanyihao; +Cc: qemu-devel
On Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch series introduces basic support for the STM32F407 SoC and
> a new STM32F4spark machine in QEMU, along with a USART device model.
>
> This series includes:
> - A new SoC model (STM32F407) with initial integration.
> - A board model called STM32F4spark to instantiate and test the SoC.
> - A USART device implementation for STM32F4xx family.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
>
> Yihao Fan (3):
> Add-the-stm32f407-SoC
> Add the STM32F4spark Machine
> Add STM32F4xx USART device model
>
> MAINTAINERS | 16 ++
> hw/arm/Kconfig | 13 ++
> hw/arm/meson.build | 2 +
> hw/arm/stm32f407_soc.c | 154 +++++++++++++++++++
> hw/arm/stm32f4spark.c | 48 ++++++
> hw/char/Kconfig | 3 +
> hw/char/meson.build | 1 +
> hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
> include/hw/arm/stm32f407_soc.h | 47 ++++++
> include/hw/char/stm32f4xx_usart.h | 60 ++++++++
For a new board model there are a couple of things we'd like
to see that aren't in this patchset:
(1) Documentation. This lives in docs/system/arm/. For
this board you want to add it to stm32.rst.
(2) A test case in tests/functional/ -- generally this is
something that downloads an image file from a public stable
URL, runs it in QEMU and checks for some output from the
guest on the UART indicating success. Lots of examples
in this directory to see how to do it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 0/3] Add STM32F4 support and USART device model
2025-08-15 17:49 ` Peter Maydell
@ 2025-08-21 13:45 ` 范艺豪
0 siblings, 0 replies; 15+ messages in thread
From: 范艺豪 @ 2025-08-21 13:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2113 bytes --]
Hi ,
Thanks for the review and helpful suggestions.
I will update the board documentation and provide a functional test case in the next version.
Best wishes,
Yihao Fan
范艺豪
fanyihao@rt-thread.org
Original:
From：Peter Maydell <peter.maydell@linaro.org>Date：2025-08-16 01:49:37(中国 (GMT+08:00))To：fanyihao<fanyihao@rt-thread.org>Cc：qemu-devel<qemu-devel@nongnu.org>Subject：Re: [PATCH v2 0/3] Add STM32F4 support and USART device modelOn Mon, 21 Jul 2025 at 21:11, <fanyihao@rt-thread.org> wrote:
>
> From: Yihao Fan <fanyihao@rt-thread.org>
>
> This patch series introduces basic support for the STM32F407 SoC and
> a new STM32F4spark machine in QEMU, along with a USART device model.
>
> This series includes:
> - A new SoC model (STM32F407) with initial integration.
> - A board model called STM32F4spark to instantiate and test the SoC.
> - A USART device implementation for STM32F4xx family.
>
> Signed-off-by: Yihao Fan <fanyihao@rt-thread.org>
>
> Yihao Fan (3):
> Add-the-stm32f407-SoC
> Add the STM32F4spark Machine
> Add STM32F4xx USART device model
>
> MAINTAINERS | 16 ++
> hw/arm/Kconfig | 13 ++
> hw/arm/meson.build | 2 +
> hw/arm/stm32f407_soc.c | 154 +++++++++++++++++++
> hw/arm/stm32f4spark.c | 48 ++++++
> hw/char/Kconfig | 3 +
> hw/char/meson.build | 1 +
> hw/char/stm32f4xx_usart.c | 236 ++++++++++++++++++++++++++++++
> include/hw/arm/stm32f407_soc.h | 47 ++++++
> include/hw/char/stm32f4xx_usart.h | 60 ++++++++
For a new board model there are a couple of things we'd like
to see that aren't in this patchset:
(1) Documentation. This lives in docs/system/arm/. For
this board you want to add it to stm32.rst.
(2) A test case in tests/functional/ -- generally this is
something that downloads an image file from a public stable
URL, runs it in QEMU and checks for some output from the
guest on the UART indicating success. Lots of examples
in this directory to see how to do it.
thanks
-- PMM
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^ permalink raw reply [flat|nested] 15+ messages in thread