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From: Bibo Mao <maobibo@loongson.cn>
To: Song Gao <gaosong@loongson.cn>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>, qemu-devel@nongnu.org
Subject: [PATCH v3 16/17] target/loongarch: Reduce TLB flush with helper_tlbwr
Date: Fri, 25 Jul 2025 09:47:39 +0800	[thread overview]
Message-ID: <20250725014739.1031030-1-maobibo@loongson.cn> (raw)
In-Reply-To: <20250725013739.994437-1-maobibo@loongson.cn>

With function helper_tlbwr(), specified LoongArch TLB entry will be
updated. There are two PTE pages in one TLB entry, it is not
necessary to flush QEMU TLB when one PTE page keeps unchanged and
ther other PTE page is newly added.

Here check whether PTE page is the same or not, TLB flush can be
skipped if both are the same or newly added.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 36 ++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 1ed2471e0a..6ac102862b 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -327,16 +327,42 @@ void helper_tlbrd(CPULoongArchState *env)
 void helper_tlbwr(CPULoongArchState *env)
 {
     int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+    LoongArchTLB *old, new;
+    int skip_inv = 0;
+    uint8_t tlb_v;
 
-    invalidate_tlb(env, index);
-
+    old = env->tlb + index;
     if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
-        env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
-                                              TLB_MISC, E, 0);
+        invalidate_tlb(env, index);
+        old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
         return;
     }
 
-    fill_tlb_entry(env, env->tlb + index);
+    new.tlb_misc = 0;
+    new.tlb_entry0 = 0;
+    new.tlb_entry1 = 0;
+    fill_tlb_entry(env, &new);
+    /* Check whether ASID/VPPN is the same */
+    if (old->tlb_misc == new.tlb_misc) {
+        tlb_v = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
+        /* Check whether even pte the same or invalid */
+        if (!tlb_v || new.tlb_entry0 == old->tlb_entry0) {
+            skip_inv = 1;
+        }
+
+        /* Check whether odd pte the same or invalid */
+        tlb_v = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
+        if (!tlb_v || new.tlb_entry1 == old->tlb_entry1) {
+            skip_inv &= 1;
+        }
+    }
+
+    if (!skip_inv) {
+        invalidate_tlb(env, index);
+    }
+    old->tlb_misc = new.tlb_misc;
+    old->tlb_entry0 = new.tlb_entry0;
+    old->tlb_entry1 = new.tlb_entry1;
 }
 
 void helper_tlbfill(CPULoongArchState *env)
-- 
2.39.3



  parent reply	other threads:[~2025-07-25  1:48 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-25  1:37 [PATCH v3 00/17] target/loongarch: Enhancement about tcg mmu Bibo Mao
2025-07-25  1:37 ` [PATCH v3 01/17] target/loongarch: Move some function definition to kvm directory Bibo Mao
2025-07-25 23:37   ` Richard Henderson
2025-07-25  1:37 ` [PATCH v3 02/17] target/loongarch: Define function loongarch_cpu_post_init as static Bibo Mao
2025-07-25 23:38   ` Richard Henderson
2025-07-25  1:37 ` [PATCH v3 03/17] target/loongarch: Set page size in TLB misc with STLB Bibo Mao
2025-07-25  1:37 ` [PATCH v3 04/17] target/loongarch: Add header file cpu-mmu.h Bibo Mao
2025-07-26  1:10   ` Richard Henderson
2025-07-26  1:16   ` Richard Henderson
2025-07-28  3:08     ` Bibo Mao
2025-07-25  1:37 ` [PATCH v3 05/17] target/loongarch: Add common function loongarch_check_pte() Bibo Mao
2025-07-26  1:19   ` Richard Henderson
2025-07-28  3:15     ` Bibo Mao
2025-07-28  5:07       ` Richard Henderson
2025-07-25  1:37 ` [PATCH v3 06/17] target/loongarch: Use loongarch_check_pte() with page table walking Bibo Mao
2025-07-26  1:20   ` Richard Henderson
2025-07-25  1:37 ` [PATCH v3 07/17] target/loongarch: Add parameter mmu_context with loongarch_page_table_walker Bibo Mao
2025-07-26  1:31   ` Richard Henderson
2025-07-28  3:16     ` Bibo Mao
2025-07-25  1:37 ` [PATCH v3 08/17] target/loongarch: Add parameter mmu_context with loongarch_map_tlb_entry Bibo Mao
2025-07-25  1:37 ` [PATCH v3 09/17] target/loongarch: Add parameter mmu_context with loongarch_get_addr_from_tlb Bibo Mao
2025-07-25  1:37 ` [PATCH v3 10/17] target/loongarch: Add parameter mmu_context with loongarch_map_address Bibo Mao
2025-07-25  1:37 ` [PATCH v3 11/17] target/loongarch: Add parameter mmu_context with get_physical_address Bibo Mao
2025-07-25  1:37 ` [PATCH v3 12/17] target/loongarch: Track user mode address accessed in kernel mode Bibo Mao
2025-07-25  1:37 ` [PATCH v3 13/17] target/loongarch: Use correct address when flush tlb Bibo Mao
2025-07-26  1:45   ` Richard Henderson
2025-07-28  3:22     ` Bibo Mao
2025-07-28  5:09       ` Richard Henderson
2025-07-28  6:05         ` Bibo Mao
2025-07-25  1:37 ` [PATCH v3 14/17] target/loongarch: Use mmu idx bitmap method " Bibo Mao
2025-07-25  1:47 ` [PATCH v3 15/17] target/loongarch: Add parameter tlb pointer with fill_tlb_entry Bibo Mao
2025-07-26  1:47   ` Richard Henderson
2025-07-25  1:47 ` Bibo Mao [this message]
2025-07-25  1:48 ` [PATCH v3 17/17] target/loongarch: Update TLB index selection method Bibo Mao

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