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From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>, Mads Ynddal <mads@ynddal.dk>,
	Alexander Graf <agraf@csgraf.de>,
	Shannon Zhao <shannon.zhaosl@gmail.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Cameron Esfahani <dirty@apple.com>,
	Roman Bolshakov <rbolshakov@ddn.com>,
	Phil Dennis-Jordan <phil@philjordan.eu>,
	qemu-arm@nongnu.org, Ani Sinha <anisinha@redhat.com>,
	Mohamed Mediouni <mohamed@unpredictable.fr>
Subject: [PATCH 4/9] target/arm: add asserts for code paths not leveraged when using the vGIC
Date: Fri, 25 Jul 2025 10:34:26 +0200	[thread overview]
Message-ID: <20250725083431.91450-5-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20250725083431.91450-1-mohamed@unpredictable.fr>

When using the vGIC, timers are directly handled by the platform, so no vmexits ought to happen in that case.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 target/arm/hvf/hvf.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index bb31df90b8..7b4e8297af 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1378,6 +1378,9 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
     case SYSREG_ICC_SGI1R_EL1:
     case SYSREG_ICC_SRE_EL1:
     case SYSREG_ICC_CTLR_EL1:
+        if (hvf_irqchip_in_kernel()) {
+            abort();
+        }
         /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
         if (hvf_sysreg_read_cp(cpu, reg, val)) {
             return 0;
@@ -1694,6 +1697,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
     case SYSREG_ICC_SGI0R_EL1:
     case SYSREG_ICC_SGI1R_EL1:
     case SYSREG_ICC_SRE_EL1:
+        if (hvf_irqchip_in_kernel()) {
+            abort();
+        }
         /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
         if (hvf_sysreg_write_cp(cpu, reg, val)) {
             return 0;
@@ -1957,6 +1963,10 @@ int hvf_vcpu_exec(CPUState *cpu)
         /* This is the main one, handle below. */
         break;
     case HV_EXIT_REASON_VTIMER_ACTIVATED:
+        /* This is only for when a user-mode irqchip is used. */
+        if (hvf_irqchip_in_kernel()) {
+            assert("vtimer activated vmexit when using platform GIC");
+        }
         qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
         cpu->accel->vtimer_masked = true;
         return 0;
-- 
2.39.5 (Apple Git-154)



  parent reply	other threads:[~2025-07-25  8:40 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-25  8:34 [PATCH 0/9] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 1/9] target/arm: hvf: stubbing writes to LORC_EL1 Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 2/9] accel, hw/arm, include/system/hvf: plumbing changes for HVF vGIC Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 3/9] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2025-07-25  8:34 ` Mohamed Mediouni [this message]
2025-07-25  8:34 ` [PATCH 5/9] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 6/9] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 7/9] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 8/9] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-07-25  8:34 ` [PATCH 9/9] target/arm: hvf: use LOG_UNIMP for CNTP_CVAL_EL0/SYSREG_CNTP_CTL_EL0 Mohamed Mediouni

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