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From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: Mads Ynddal <mads@ynddal.dk>,
	qemu-arm@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Ani Sinha <anisinha@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Cameron Esfahani <dirty@apple.com>,
	Phil Dennis-Jordan <phil@philjordan.eu>,
	Peter Maydell <peter.maydell@linaro.org>,
	Alexander Graf <agraf@csgraf.de>,
	Shannon Zhao <shannon.zhaosl@gmail.com>,
	Roman Bolshakov <rbolshakov@ddn.com>,
	Mohamed Mediouni <mohamed@unpredictable.fr>
Subject: [PATCH v2 9/9] target/arm: hvf: use LOG_UNIMP for CNTP_CVAL_EL0/SYSREG_CNTP_CTL_EL0
Date: Fri, 25 Jul 2025 10:55:45 +0200	[thread overview]
Message-ID: <20250725085545.93619-10-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr>

Instead of considering reads there to be fatal, mark it as unimplemented.

This is to allow experimentation on using configurations other than the Apple vGIC.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 target/arm/hvf/hvf.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 5344e23db1..d01b9b4dcd 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -300,6 +300,7 @@ void hvf_arm_init_debug(void)
 /* EL2 registers */
 #define SYSREG_CNTHCTL_EL2    SYSREG(3, 4, 14, 1, 0)
 #define SYSREG_MDCCINT_EL1    SYSREG(2, 0, 0, 2, 0)
+#define SYSREG_CNTP_CVAL_EL0   SYSREG(3, 3, 14, 2, 2)
 
 #define WFX_IS_WFE (1 << 0)
 
@@ -1396,6 +1397,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
     case SYSREG_CNTHCTL_EL2:
         assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));
         return 0;
+    case SYSREG_CNTP_CTL_EL0:
+        qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CTL_EL0\n");
+        return 0;
+    case SYSREG_CNTP_CVAL_EL0:
+        qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CVAL_EL0\n");
+        return 0;
     case SYSREG_MDCCINT_EL1:
         assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));
         return 0;
@@ -1712,6 +1719,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
          */
         qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n");
         return 0;
+    case SYSREG_CNTP_CVAL_EL0:
+        qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CVAL_EL0\n");
+        return 0;
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         return 0;
-- 
2.39.5 (Apple Git-154)



  parent reply	other threads:[~2025-07-25  8:57 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-25  8:55 [PATCH v2 0/9] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 1/9] target/arm: hvf: stubbing writes to LORC_EL1 Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 2/9] accel, hw/arm, include/system/hvf: plumbing changes for HVF vGIC Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 3/9] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 4/9] target/arm: add asserts for code paths not leveraged when using the vGIC Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 5/9] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 6/9] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 7/9] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Mohamed Mediouni
2025-07-25  8:55 ` [PATCH v2 8/9] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-07-25  8:55 ` Mohamed Mediouni [this message]
2025-07-25  9:27 ` [PATCH v2 0/9] HVF: Add support for platform vGIC and nested virtualisation Mads Ynddal

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