From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: Mads Ynddal <mads@ynddal.dk>,
qemu-arm@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Ani Sinha <anisinha@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Cameron Esfahani <dirty@apple.com>,
Phil Dennis-Jordan <phil@philjordan.eu>,
Peter Maydell <peter.maydell@linaro.org>,
Alexander Graf <agraf@csgraf.de>,
Shannon Zhao <shannon.zhaosl@gmail.com>,
Roman Bolshakov <rbolshakov@ddn.com>,
Mohamed Mediouni <mohamed@unpredictable.fr>
Subject: [PATCH v2 7/9] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1
Date: Fri, 25 Jul 2025 10:55:43 +0200 [thread overview]
Message-ID: <20250725085545.93619-8-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr>
HVF traps accesses to CNTHCTL_EL2. For nested guests, HVF traps accesses to MDCCINT_EL1.
Pass through those accesses to the Hypervisor.framework library.
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
target/arm/hvf/hvf.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index c32e6ab289..5344e23db1 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -21,6 +21,7 @@
#include "cpregs.h"
#include "cpu-sysregs.h"
+#include <Hypervisor/hv_vcpu_types.h>
#include <mach/mach_time.h>
#include "system/address-spaces.h"
@@ -296,6 +297,10 @@ void hvf_arm_init_debug(void)
#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
+/* EL2 registers */
+#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0)
+#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0)
+
#define WFX_IS_WFE (1 << 0)
#define TMR_CTL_ENABLE (1 << 0)
@@ -1388,6 +1393,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTHCTL_EL2:
+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));
+ return 0;
+ case SYSREG_MDCCINT_EL1:
+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));
+ return 0;
case SYSREG_ICC_AP0R0_EL1:
case SYSREG_ICC_AP0R1_EL1:
case SYSREG_ICC_AP0R2_EL1:
@@ -1704,6 +1715,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTHCTL_EL2:
+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));
+ return 0;
+ case SYSREG_MDCCINT_EL1:
+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));
+ return 0;
case SYSREG_LORC_EL1:
/* Dummy register */
return 0;
--
2.39.5 (Apple Git-154)
next prev parent reply other threads:[~2025-07-25 8:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-25 8:55 [PATCH v2 0/9] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 1/9] target/arm: hvf: stubbing writes to LORC_EL1 Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 2/9] accel, hw/arm, include/system/hvf: plumbing changes for HVF vGIC Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 3/9] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 4/9] target/arm: add asserts for code paths not leveraged when using the vGIC Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 5/9] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 6/9] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2025-07-25 8:55 ` Mohamed Mediouni [this message]
2025-07-25 8:55 ` [PATCH v2 8/9] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-07-25 8:55 ` [PATCH v2 9/9] target/arm: hvf: use LOG_UNIMP for CNTP_CVAL_EL0/SYSREG_CNTP_CTL_EL0 Mohamed Mediouni
2025-07-25 9:27 ` [PATCH v2 0/9] HVF: Add support for platform vGIC and nested virtualisation Mads Ynddal
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