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[98.150.199.49]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fbe333efesm30016415ad.65.2025.07.27.01.03.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 01:03:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 25/82] include/hw/core/cpu: Invert the indexing into CPUTLBDescFast Date: Sat, 26 Jul 2025 22:01:57 -1000 Message-ID: <20250727080254.83840-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250727080254.83840-1-richard.henderson@linaro.org> References: <20250727080254.83840-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This array is within CPUNegativeOffsetState, which means the last element of the array has an offset from env with the smallest magnitude. This can be encoded into fewer bits when generating TCG fast path memory references. When we changed the NB_MMU_MODES to be a global constant, rather than a per-target value, we pessimized the code generated for targets which use only a few mmu indexes. By inverting the array index, we counteract that. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 6 +++++- tcg/tcg.c | 3 ++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bd835b07d5..85b1ab4022 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -596,7 +596,11 @@ static inline CPUArchState *cpu_env(CPUState *cpu) #ifdef CONFIG_TCG static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *cpu, int mmu_idx) { - return &cpu->neg.tlb.f[mmu_idx]; + /* + * Invert the index order of the CPUTLBDescFast array so that lower + * mmu_idx have negative offsets from env with smaller absolute values. + */ + return &cpu->neg.tlb.f[NB_MMU_MODES - 1 - mmu_idx]; } #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index afac55a203..615675d185 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -425,7 +425,8 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) static int __attribute__((unused)) tlb_mask_table_ofs(TCGContext *s, int which) { - return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - + /* Invert the index order -- see cpu_tlb_fast. */ + return (offsetof(CPUNegativeOffsetState, tlb.f[NB_MMU_MODES - 1 - which]) - sizeof(CPUNegativeOffsetState)); } -- 2.43.0