From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 77/82] linux-user/aarch64: Generate GCS signal records
Date: Sat, 26 Jul 2025 22:02:49 -1000 [thread overview]
Message-ID: <20250727080254.83840-78-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250727080254.83840-1-richard.henderson@linaro.org>
Here we must push and pop a cap on the GCS stack as
well as the gcs record on the normal stack.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 129 ++++++++++++++++++++++++++++++++++--
1 file changed, 123 insertions(+), 6 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index ef97be3ac7..a1957a330c 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -22,6 +22,7 @@
#include "signal-common.h"
#include "linux-user/trace.h"
#include "target/arm/cpu-features.h"
+#include "gcs-internal.h"
struct target_sigcontext {
uint64_t fault_address;
@@ -152,6 +153,16 @@ struct target_zt_context {
QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES != \
sizeof_field(CPUARMState, za_state.zt0));
+#define TARGET_GCS_MAGIC 0x47435300
+#define GCS_SIGNAL_CAP(X) ((X) & TARGET_PAGE_MASK)
+
+struct target_gcs_context {
+ struct target_aarch64_ctx head;
+ uint64_t gcspr;
+ uint64_t features_enabled;
+ uint64_t reserved;
+};
+
struct target_rt_sigframe {
struct target_siginfo info;
struct target_ucontext uc;
@@ -322,6 +333,35 @@ static void target_setup_zt_record(struct target_zt_context *zt,
}
}
+static bool target_setup_gcs_record(struct target_gcs_context *ctx,
+ CPUARMState *env, uint64_t return_addr)
+{
+ uint64_t mode = gcs_get_el0_mode(env);
+ uint64_t gcspr = env->cp15.gcspr_el[0];
+
+ if (mode & PR_SHADOW_STACK_ENABLE) {
+ /* Push a cap for the signal frame. */
+ gcspr -= 8;
+ if (put_user_u64(GCS_SIGNAL_CAP(gcspr), gcspr)) {
+ return false;
+ }
+
+ /* Push a gcs entry for the trampoline. */
+ if (put_user_u64(return_addr, gcspr - 8)) {
+ return false;
+ }
+ env->cp15.gcspr_el[0] = gcspr - 8;
+ }
+
+ __put_user(TARGET_GCS_MAGIC, &ctx->head.magic);
+ __put_user(sizeof(*ctx), &ctx->head.size);
+ __put_user(gcspr, &ctx->gcspr);
+ __put_user(mode, &ctx->features_enabled);
+ __put_user(0, &ctx->reserved);
+
+ return true;
+}
+
static void target_restore_general_frame(CPUARMState *env,
struct target_rt_sigframe *sf)
{
@@ -502,6 +542,55 @@ static bool target_restore_zt_record(CPUARMState *env,
return true;
}
+static bool target_restore_gcs_record(CPUARMState *env,
+ struct target_gcs_context *ctx,
+ bool *rebuild_hflags)
+{
+ TaskState *ts = get_task_state(env_cpu(env));
+ uint64_t cur_mode = gcs_get_el0_mode(env);
+ uint64_t new_mode, gcspr;
+
+ __get_user(new_mode, &ctx->features_enabled);
+ __get_user(gcspr, &ctx->gcspr);
+
+ if (new_mode & ~(PR_SHADOW_STACK_ENABLE |
+ PR_SHADOW_STACK_WRITE |
+ PR_SHADOW_STACK_PUSH)) {
+ return false;
+ }
+ if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) {
+ return false;
+ }
+ if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) {
+ return false;
+ }
+
+ if (new_mode & PR_SHADOW_STACK_ENABLE) {
+ uint64_t cap;
+
+ /* Pop and clear the signal cap. */
+ if (get_user_u64(cap, gcspr)) {
+ return false;
+ }
+ if (cap != GCS_SIGNAL_CAP(gcspr)) {
+ return false;
+ }
+ if (put_user_u64(0, gcspr)) {
+ return false;
+ }
+ gcspr += 8;
+ } else {
+ new_mode = 0;
+ }
+
+ env->cp15.gcspr_el[0] = gcspr;
+ if (new_mode != cur_mode) {
+ *rebuild_hflags = true;
+ gcs_set_el0_mode(env, new_mode);
+ }
+ return true;
+}
+
static int target_restore_sigframe(CPUARMState *env,
struct target_rt_sigframe *sf)
{
@@ -511,8 +600,10 @@ static int target_restore_sigframe(CPUARMState *env,
struct target_za_context *za = NULL;
struct target_tpidr2_context *tpidr2 = NULL;
struct target_zt_context *zt = NULL;
+ struct target_gcs_context *gcs = NULL;
uint64_t extra_datap = 0;
bool used_extra = false;
+ bool rebuild_hflags = false;
int sve_size = 0;
int za_size = 0;
int zt_size = 0;
@@ -582,6 +673,15 @@ static int target_restore_sigframe(CPUARMState *env,
zt_size = size;
break;
+ case TARGET_GCS_MAGIC:
+ if (gcs
+ || size != sizeof(struct target_gcs_context)
+ || !cpu_isar_feature(aa64_gcs, env_archcpu(env))) {
+ goto err;
+ }
+ gcs = (struct target_gcs_context *)ctx;
+ break;
+
case TARGET_EXTRA_MAGIC:
if (extra || size != sizeof(struct target_extra_context)) {
goto err;
@@ -612,6 +712,10 @@ static int target_restore_sigframe(CPUARMState *env,
goto err;
}
+ if (gcs && !target_restore_gcs_record(env, gcs, &rebuild_hflags)) {
+ goto err;
+ }
+
/* SVE data, if present, overwrites FPSIMD data. */
if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
goto err;
@@ -631,6 +735,9 @@ static int target_restore_sigframe(CPUARMState *env,
}
if (env->svcr != svcr) {
env->svcr = svcr;
+ rebuild_hflags = true;
+ }
+ if (rebuild_hflags) {
arm_rebuild_hflags(env);
}
unlock_user(extra, extra_datap, 0);
@@ -701,7 +808,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
uc.tuc_mcontext.__reserved),
};
int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0, tpidr2_ofs = 0;
- int zt_ofs = 0, esr_ofs = 0;
+ int zt_ofs = 0, esr_ofs = 0, gcs_ofs = 0;
int sve_size = 0, za_size = 0, tpidr2_size = 0, zt_size = 0;
struct target_rt_sigframe *frame;
struct target_rt_frame_record *fr;
@@ -720,6 +827,11 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
&layout);
}
+ if (env->cp15.gcspr_el[0]) {
+ gcs_ofs = alloc_sigframe_space(sizeof(struct target_gcs_context),
+ &layout);
+ }
+
/* SVE state needs saving only if it exists. */
if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
cpu_isar_feature(aa64_sme, env_archcpu(env))) {
@@ -779,6 +891,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
goto give_sigsegv;
}
+ if (ka->sa_flags & TARGET_SA_RESTORER) {
+ return_addr = ka->sa_restorer;
+ } else {
+ return_addr = default_rt_sigreturn;
+ }
+
target_setup_general_frame(frame, env, set);
target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env);
if (esr_ofs) {
@@ -786,6 +904,10 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
/* Leave ESR_EL1 clear while it's not relevant. */
env->cp15.esr_el[1] = 0;
}
+ if (gcs_ofs &&
+ !target_setup_gcs_record((void *)frame + gcs_ofs, env, return_addr)) {
+ goto give_sigsegv;
+ }
target_setup_end_record((void *)frame + layout.std_end_ofs);
if (layout.extra_ofs) {
target_setup_extra_record((void *)frame + layout.extra_ofs,
@@ -811,11 +933,6 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
__put_user(env->xregs[29], &fr->fp);
__put_user(env->xregs[30], &fr->lr);
- if (ka->sa_flags & TARGET_SA_RESTORER) {
- return_addr = ka->sa_restorer;
- } else {
- return_addr = default_rt_sigreturn;
- }
env->xregs[0] = usig;
env->xregs[29] = frame_addr + fr_ofs;
env->xregs[30] = return_addr;
--
2.43.0
next prev parent reply other threads:[~2025-07-27 8:13 UTC|newest]
Thread overview: 188+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-27 8:01 [PATCH for-10.2 00/82] target/arm: Implement FEAT_GCS Richard Henderson
2025-07-27 8:01 ` [PATCH 01/82] target/arm: Add prot_check parameter to pmsav8_mpu_lookup Richard Henderson
2025-07-30 20:27 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 02/82] target/arm: Add in_prot_check to S1Translate Richard Henderson
2025-07-30 20:27 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 03/82] target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug Richard Henderson
2025-07-30 20:28 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 04/82] target/arm: Introduce get_phys_addr_for_at Richard Henderson
2025-07-30 20:29 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 05/82] target/arm: Skip AF and DB updates for AccessType_AT Richard Henderson
2025-07-30 20:31 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 06/82] target/arm: Add prot_check parameter to do_ats_write Richard Henderson
2025-07-30 20:35 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 07/82] target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5 Richard Henderson
2025-07-30 20:35 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 08/82] target/arm: Remove outdated comment for ZCR_EL12 Richard Henderson
2025-07-30 20:36 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 09/82] target/arm: Implement FEAT_ATS1A Richard Henderson
2025-07-30 20:38 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 10/82] target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE Richard Henderson
2025-07-30 20:38 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 11/82] target/arm: Enable TCR2_ELx.PIE Richard Henderson
2025-07-30 20:39 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 12/82] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Richard Henderson
2025-07-30 20:41 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 13/82] target/arm: Force HPD for stage2 translations Richard Henderson
2025-07-30 20:42 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 14/82] target/arm: Cache NV1 early in get_phys_addr_lpae Richard Henderson
2025-07-30 20:43 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 15/82] target/arm: Populate PIE in aa64_va_parameters Richard Henderson
2025-07-30 20:45 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 16/82] target/arm: Implement get_S1prot_indirect Richard Henderson
2025-07-31 21:15 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 17/82] target/arm: Implement get_S2prot_indirect Richard Henderson
2025-07-31 21:13 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 18/82] target/arm: Do not migrate env->exception Richard Henderson
2025-07-30 20:46 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 19/82] target/arm: Expand CPUARMState.exception.syndrome to 64 bits Richard Henderson
2025-07-30 20:47 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 20/82] target/arm: Expand syndrome parameter to raise_exception* Richard Henderson
2025-07-30 20:47 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 21/82] target/arm: Implement dirtybit check for PIE Richard Henderson
2025-07-30 20:50 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 22/82] target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max Richard Henderson
2025-07-30 20:50 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 23/82] include/hw/core/cpu: Introduce MMUIdxMap Richard Henderson
2025-07-30 20:52 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 24/82] include/hw/core/cpu: Introduce cpu_tlb_fast Richard Henderson
2025-07-30 20:53 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 25/82] include/hw/core/cpu: Invert the indexing into CPUTLBDescFast Richard Henderson
2025-07-30 21:00 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 26/82] target/hppa: Adjust mmu indexes to begin with 0 Richard Henderson
2025-07-30 21:03 ` Pierrick Bouvier
2025-07-27 8:01 ` [PATCH 27/82] include/exec/memopidx: Adjust for 32 mmu indexes Richard Henderson
2025-07-30 21:03 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 28/82] include/hw/core/cpu: Widen MMUIdxMap Richard Henderson
2025-07-30 21:07 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 29/82] target/arm: Split out mmuidx.h from cpu.h Richard Henderson
2025-07-30 21:07 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 30/82] target/arm: Convert arm_mmu_idx_to_el from switch to table Richard Henderson
2025-07-30 21:10 ` Pierrick Bouvier
2025-07-30 21:12 ` Pierrick Bouvier
2025-07-30 21:31 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 31/82] target/arm: Remove unused env argument from regime_el Richard Henderson
2025-07-30 21:13 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 32/82] target/arm: Convert regime_el from switch to table Richard Henderson
2025-07-30 21:15 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 33/82] target/arm: Convert regime_has_2_ranges " Richard Henderson
2025-07-30 21:16 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 34/82] target/arm: Remove unused env argument from regime_is_pan Richard Henderson
2025-07-30 21:17 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 35/82] target/arm: Convert regime_is_pan from switch to table Richard Henderson
2025-07-30 21:17 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 36/82] target/arm: Remove unused env argument from regime_is_user Richard Henderson
2025-07-30 21:18 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 37/82] target/arm: Convert regime_is_user from switch to table Richard Henderson
2025-07-30 21:21 ` Pierrick Bouvier
2025-08-01 3:53 ` Richard Henderson
2025-08-01 16:10 ` Pierrick Bouvier
2025-08-01 18:06 ` Peter Maydell
2025-07-27 8:02 ` [PATCH 38/82] target/arm: Convert arm_mmu_idx_is_stage1_of_2 " Richard Henderson
2025-07-30 21:23 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 39/82] target/arm: Convert regime_is_stage2 " Richard Henderson
2025-07-30 21:23 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 40/82] target/arm: Introduce mmu indexes for GCS Richard Henderson
2025-07-30 21:28 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 41/82] target/arm: Introduce regime_to_gcs Richard Henderson
2025-07-30 21:33 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 42/82] target/arm: Support page protections for GCS mmu indexes Richard Henderson
2025-07-31 18:40 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 43/82] target/arm: Implement gcs bit for data abort Richard Henderson
2025-07-31 18:41 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 44/82] target/arm: Add GCS cpregs Richard Henderson
2025-07-31 18:45 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 45/82] target/arm: Add GCS enable and trap levels to DisasContext Richard Henderson
2025-07-31 18:54 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 46/82] target/arm: Implement FEAT_CHK Richard Henderson
2025-07-29 16:01 ` Gustavo Romero
2025-07-29 17:21 ` Richard Henderson
2025-07-31 18:59 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 47/82] target/arm: Expand pstate to 64 bits Richard Henderson
2025-07-31 19:13 ` Pierrick Bouvier
2025-08-01 4:24 ` Richard Henderson
2025-08-01 12:35 ` Manos Pitsidianakis
2025-08-01 4:29 ` Richard Henderson
2025-08-01 16:12 ` Pierrick Bouvier
2025-08-01 20:19 ` Richard Henderson
2025-08-01 13:22 ` Peter Maydell
2025-08-01 16:26 ` Pierrick Bouvier
2025-08-01 16:37 ` Peter Maydell
2025-08-01 16:41 ` Pierrick Bouvier
2025-08-01 16:44 ` Peter Maydell
2025-08-01 16:53 ` Pierrick Bouvier
2025-08-01 16:55 ` Pierrick Bouvier
2025-08-01 18:45 ` Manos Pitsidianakis
2025-08-02 3:14 ` Thiago Jung Bauermann
2025-08-01 20:22 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 48/82] target/arm: Add syndrome data for EC_GCS Richard Henderson
2025-07-31 19:35 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 49/82] target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx Richard Henderson
2025-07-31 20:53 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 50/82] target/arm: Split {arm,core}_user_mem_index Richard Henderson
2025-07-31 21:06 ` Pierrick Bouvier
2025-07-31 21:24 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 51/82] target/arm: Introduce delay_exception{_el} Richard Henderson
2025-07-31 21:09 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 52/82] target/arm: Emit HSTR trap exception out of line Richard Henderson
2025-07-31 21:10 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 53/82] target/arm: Emit v7m LTPSIZE " Richard Henderson
2025-07-31 21:10 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 54/82] target/arm: Implement GCSSTR, GCSSTTR Richard Henderson
2025-07-31 21:25 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 55/82] target/arm: Implement GCSB Richard Henderson
2025-07-31 21:27 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 56/82] target/arm: Implement GCSPUSHM Richard Henderson
2025-07-31 21:33 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 57/82] target/arm: Implement GCSPOPM Richard Henderson
2025-07-31 21:34 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 58/82] target/arm: Implement GCSPUSHX Richard Henderson
2025-07-31 21:36 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 59/82] target/arm: Implement GCSPOPX Richard Henderson
2025-07-31 21:37 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 60/82] target/arm: Implement GCSPOPCX Richard Henderson
2025-07-31 21:38 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 61/82] target/arm: Implement GCSSS1 Richard Henderson
2025-07-31 21:43 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 62/82] target/arm: Implement GCSSS2 Richard Henderson
2025-07-31 21:45 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 63/82] target/arm: Add gcs record for BL Richard Henderson
2025-07-31 21:45 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 64/82] target/arm: Add gcs record for BLR Richard Henderson
2025-07-31 21:46 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 65/82] target/arm: Add gcs record for BLR with PAuth Richard Henderson
2025-07-31 21:46 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 66/82] target/arm: Load gcs record for RET Richard Henderson
2025-07-31 21:47 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 67/82] target/arm: Load gcs record for RET with PAuth Richard Henderson
2025-07-31 21:48 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 68/82] target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL Richard Henderson
2025-07-31 21:48 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 69/82] target/arm: Implement EXLOCK check during exception return Richard Henderson
2025-07-31 21:49 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 70/82] target/arm: Enable FEAT_GCS with -cpu max Richard Henderson
2025-07-31 21:49 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 71/82] linux-user/aarch64: Implement prctls for GCS Richard Henderson
2025-07-31 21:53 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 72/82] linux-user/aarch64: Allocate new gcs stack on clone Richard Henderson
2025-07-31 21:54 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 73/82] linux-user/aarch64: Release gcs stack on thread exit Richard Henderson
2025-07-31 21:54 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 74/82] linux-user/aarch64: Implement map_shadow_stack syscall Richard Henderson
2025-07-31 21:55 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 75/82] target/arm: Enable GCSPR_EL0 for read in user-mode Richard Henderson
2025-07-31 21:56 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 76/82] linux-user/aarch64: Inject SIGSEGV for GCS faults Richard Henderson
2025-07-31 21:56 ` Pierrick Bouvier
2025-07-27 8:02 ` Richard Henderson [this message]
2025-07-31 21:57 ` [PATCH 77/82] linux-user/aarch64: Generate GCS signal records Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 78/82] linux-user: Change exported get_elf_hwcap to abi_ulong Richard Henderson
2025-07-31 21:58 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 79/82] linux-user/aarch64: Enable GCS in HWCAP Richard Henderson
2025-07-31 21:58 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 80/82] tests/tcg/aarch64: Add gcsstr Richard Henderson
2025-07-31 22:05 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 81/82] tests/tcg/aarch64: Add gcspushm Richard Henderson
2025-07-31 22:11 ` Pierrick Bouvier
2025-07-27 8:02 ` [PATCH 82/82] tests/tcg/aarch64: Add gcsss Richard Henderson
2025-07-31 22:14 ` Pierrick Bouvier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250727080254.83840-78-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).