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* [PULL 00/11] riscv-to-apply queue
@ 2025-07-30  1:01 alistair23
  2025-07-30  1:01 ` [PULL 01/11] target/riscv: Fix pmp range wraparound on zero alistair23
                   ` (13 more replies)
  0 siblings, 14 replies; 20+ messages in thread
From: alistair23 @ 2025-07-30  1:01 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e:

  Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250730-2

for you to fetch changes up to 86bc3a0abf10072081cddd8dff25aa72c60e67b8:

  target/riscv: Restrict midelegh access to S-mode harts (2025-07-30 10:59:26 +1000)

----------------------------------------------------------------
Third RISC-V PR for 10.1

* Fix pmp range wraparound on zero
* Update FADT and MADT versions in ACPI tables
* Fix target register read when source is inactive
* Add riscv_hwprobe entry to linux-user strace list
* Do not call GETPC() in check_ret_from_m_mode()
* Revert "Generate strided vector loads/stores with tcg nodes."
* Fix exception type when VU accesses supervisor CSRs
* Restrict mideleg/medeleg/medelegh access to S-mode harts
* Restrict midelegh access to S-mode harts

----------------------------------------------------------------
Daniel Henrique Barboza (3):
      linux-user/strace.list: add riscv_hwprobe entry
      target/riscv: do not call GETPC() in check_ret_from_m_mode()
      riscv: Revert "Generate strided vector loads/stores with tcg nodes."

Jay Chang (2):
      target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
      target/riscv: Restrict midelegh access to S-mode harts

Sunil V L (3):
      bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
      hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
      tests/data/acpi/riscv64: Update expected FADT and MADT

Vac Chen (1):
      target/riscv: Fix pmp range wraparound on zero

Xu Lu (1):
      target/riscv: Fix exception type when VU accesses supervisor CSRs

Yang Jialong (1):
      intc/riscv_aplic: Fix target register read when source is inactive

 hw/intc/riscv_aplic.c                   |   6 +-
 hw/riscv/virt-acpi-build.c              |  25 +--
 target/riscv/csr.c                      |  15 +-
 target/riscv/op_helper.c                |  15 +-
 target/riscv/pmp.c                      |   7 +-
 target/riscv/insn_trans/trans_rvv.c.inc | 323 +++++---------------------------
 linux-user/strace.list                  |   3 +
 tests/data/acpi/riscv64/virt/APIC       | Bin 116 -> 116 bytes
 tests/data/acpi/riscv64/virt/FACP       | Bin 276 -> 276 bytes
 9 files changed, 90 insertions(+), 304 deletions(-)


^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PULL 00/11] riscv-to-apply queue
@ 2021-07-12 22:53 Alistair Francis
  2021-07-13 18:00 ` Peter Maydell
  0 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2021-07-12 22:53 UTC (permalink / raw)
  To: peter.maydell, qemu-devel; +Cc: Alistair Francis

The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:

  Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into staging (2021-07-12 19:15:11 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712

for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:

  hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates

----------------------------------------------------------------
Alistair Francis (3):
      char: ibex_uart: Update the register layout
      hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
      hw/riscv: opentitan: Add the flash alias

Bin Meng (7):
      target/riscv: pmp: Fix some typos
      target/riscv: csr: Remove redundant check in fp csr read/write routines
      docs/system: riscv: Fix CLINT name in the sifive_u doc
      docs/system: riscv: Add documentation for virt machine
      docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
      hw/riscv: sifive_u: Correct the CLINT timebase frequency
      hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Jose Martins (1):
      target/riscv: hardwire bits in hideleg and hedeleg

 docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
 docs/system/riscv/sifive_u.rst             |   2 +-
 docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
 docs/system/target-riscv.rst               |   1 +
 include/hw/riscv/opentitan.h               |   3 +
 hw/char/ibex_uart.c                        |  19 ++--
 hw/riscv/opentitan.c                       |   9 ++
 hw/riscv/sifive_u.c                        |  12 ++-
 target/riscv/csr.c                         |  37 +++-----
 target/riscv/pmp.c                         |  10 +--
 10 files changed, 233 insertions(+), 52 deletions(-)
 create mode 100644 docs/system/riscv/virt.rst


^ permalink raw reply	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2025-07-31  6:40 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-30  1:01 [PULL 00/11] riscv-to-apply queue alistair23
2025-07-30  1:01 ` [PULL 01/11] target/riscv: Fix pmp range wraparound on zero alistair23
2025-07-30  1:01 ` [PULL 02/11] bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes alistair23
2025-07-30  1:01 ` [PULL 03/11] hw/riscv/virt-acpi-build.c: Update FADT and MADT versions alistair23
2025-07-30  1:01 ` [PULL 04/11] tests/data/acpi/riscv64: Update expected FADT and MADT alistair23
2025-07-30  1:01 ` [PULL 05/11] intc/riscv_aplic: Fix target register read when source is inactive alistair23
2025-07-30  1:01 ` [PULL 06/11] linux-user/strace.list: add riscv_hwprobe entry alistair23
2025-07-30  1:01 ` [PULL 07/11] target/riscv: do not call GETPC() in check_ret_from_m_mode() alistair23
2025-07-30  1:01 ` [PULL 08/11] riscv: Revert "Generate strided vector loads/stores with tcg nodes." alistair23
2025-07-30  1:01 ` [PULL 09/11] target/riscv: Fix exception type when VU accesses supervisor CSRs alistair23
2025-07-30  1:01 ` [PULL 10/11] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts alistair23
2025-07-30  1:01 ` [PULL 11/11] target/riscv: Restrict midelegh " alistair23
2025-07-30  1:04 ` [PULL 00/11] riscv-to-apply queue Alistair Francis
2025-07-30 15:15 ` Stefan Hajnoczi
2025-07-30 18:19 ` Michael Tokarev
2025-07-31  4:36   ` Alistair Francis
2025-07-31  6:11     ` Michael Tokarev
  -- strict thread matches above, loose matches on Subject: below --
2021-07-12 22:53 Alistair Francis
2021-07-13 18:00 ` Peter Maydell
2021-07-15  6:56   ` Alistair Francis

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