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Tsirkin" To: peng guo Cc: marcel.apfelbaum@gmail.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, wyguopeng@163.com Subject: Re: [PATCH] hw/i386/pc: Avoid overlap between CXL window and PCI 64bit BARs in QEMU Message-ID: <20250801081408-mutt-send-email-mst@kernel.org> References: <20250718133545.5261-1-engguopeng@buaa.edu.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250718133545.5261-1-engguopeng@buaa.edu.cn> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Jul 18, 2025 at 09:35:45PM +0800, peng guo wrote: > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the > 9p device fails to initialize properly. The kernel reports the following: > > virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1 > 9pnet_virtio virtio0: probe with driver 9pnet_virtio failed with error -22 > > Further investigation revealed that the 64-bit BAR space assigned to the 9pnet > device was overlapped by the memory window allocated for the CXL devices. As a > result, the kernel could not correctly access the BAR region, causing the > virtio device to malfunction. > > An excerpt from /proc/iomem shows: > > 480010000-cffffffff : CXL Window 0 > 480010000-4bfffffff : PCI Bus 0000:00 > 4c0000000-4c01fffff : PCI Bus 0000:0c > 4c0000000-4c01fffff : PCI Bus 0000:0d > 4c0200000-cffffffff : PCI Bus 0000:00 > 4c0200000-4c0203fff : 0000:00:03.0 > 4c0200000-4c0203fff : virtio-pci-modern > > To address this issue, this patch uses the value of `cxl_resv_end` to reserve > sufficient address space and ensure that CXL memory windows are allocated > beyond all PCI 64-bit BARs. This prevents overlap with 64-bit BARs regions such > as those used by virtio or other pcie devices, resolving the conflict. > > QEMU Build Configuration: > > ./configure --prefix=/home/work/qemu_master/build/ \ > --target-list=x86_64-softmmu \ > --enable-kvm \ > --enable-virtfs > > QEMU Boot Command: > > sudo /home/work/qemu_master/qemu/build/qemu-system-x86_64 \ > -nographic -machine q35,cxl=on -enable-kvm -m 16G -smp 8 \ > -hda /home/work/gp_qemu/rootfs.img \ > -virtfs local,path=/home/work/gp_qemu/share,mount_tag=host0,security_model=passthrough,id=host0 \ > -kernel /home/work/linux_output/arch/x86/boot/bzImage \ > --append "console=ttyS0 crashkernel=256M root=/dev/sda rootfstype=ext4 rw loglevel=8" \ > -object memory-backend-ram,id=vmem0,share=on,size=4096M \ > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0,sn=0x123456789 \ > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G > > Tested in a QEMU setup with a CXL Type 3 device and a 9pnet virtio device. > > Signed-off-by: peng guo To clarify I am expecting a new version of this. > --- > hw/i386/pc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 2f58e73d3347..180bc615f3f0 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -975,7 +975,7 @@ void pc_memory_init(PCMachineState *pcms, > > rom_set_fw(fw_cfg); > > - if (machine->device_memory) { > + if (machine->device_memory || cxl_resv_end) { > uint64_t *val = g_malloc(sizeof(*val)); > uint64_t res_mem_end; > > -- > 2.43.0