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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3ac574sm41205758f8f.5.2025.08.11.10.06.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 11 Aug 2025 10:06:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Miguel Luis , Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Paolo Bonzini , Haibo Xu , Mohamed Mediouni , Mark Burton , Alexander Graf , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Mads Ynddal , Eric Auger , qemu-arm@nongnu.org, Cameron Esfahani , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 00/11] target/arm: Introduce host_cpu_feature_supported() API Date: Mon, 11 Aug 2025 19:06:00 +0200 Message-ID: <20250811170611.37482-1-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, Mohamed and myself are working on adding nested virtualization support to HVF Aarch64. Mohamed approach leverages the latest hardware features of the Apple M3+ Silicon chips [1], while mine falls back to emulation [2] when features are not available, as it happens with the M1 and M2 chipsets. We want to support both methods long term, as they solve different use cases. Therefore I'm looking for a common API for methods added in both series. In this series we propose the host_cpu_feature_supported() method to check if a feature is supported by the host, allowing fall back to TCG. KVM uses are converted, and an example -- while not really usable without other patch applied -- is provided for HVF. Does this look reasonable enough to pursue in that direction? Thanks, Phil. [1] https://lore.kernel.org/qemu-devel/20250808070137.48716-1-mohamed@unpredictable.fr/ [2] https://lore.kernel.org/qemu-devel/20250620172751.94231-1-philmd@linaro.org/ Mohamed Mediouni (2): target/arm: Factor hvf_psci_get_target_el() out target/arm/hvf: Sync registers used at EL2 Philippe Mathieu-Daudé (9): accel/system: Introduce hwaccel_enabled() helper target/arm: Use generic hwaccel_enabled() to check 'host' cpu type target/arm: Restrict PMU to system mode target/arm: Introduce arm_hw_accel_cpu_feature_supported() target/arm: Introduce host_cpu_feature_supported() target/arm: Replace kvm_arm_pmu_supported by host_cpu_feature_supported target/arm: Replace kvm_arm_el2_supported by host_cpu_feature_supported target/arm/hvf: Consider EL2 acceleration for Silicon M3+ chipsets target/arm/hvf: Allow EL2/EL3 emulation on Silicon M1 / M2 include/system/hw_accel.h | 13 +++++++ target/arm/cpu.h | 23 +++++++++++++ target/arm/kvm_arm.h | 24 ------------- hw/arm/virt.c | 8 +---- target/arm/arm-qmp-cmds.c | 5 +-- target/arm/arm_hw_accel.c | 27 +++++++++++++++ target/arm/cpu.c | 14 ++++---- target/arm/cpu64.c | 11 +++--- target/arm/hvf/hvf.c | 71 +++++++++++++++++++++++++++++++++++++-- target/arm/kvm-stub.c | 10 ------ target/arm/kvm.c | 33 +++++++++++++----- target/arm/meson.build | 2 +- 12 files changed, 176 insertions(+), 65 deletions(-) create mode 100644 target/arm/arm_hw_accel.c -- 2.49.0