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From: Kane Chen via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Jamin Lin" <jamin_lin@aspeedtech.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com, Kane-Chen-AS <kane_chen@aspeedtech.com>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
Date: Tue, 12 Aug 2025 17:40:00 +0800	[thread overview]
Message-ID: <20250812094011.2617526-4-kane_chen@aspeedtech.com> (raw)
In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com>

From: Kane-Chen-AS <kane_chen@aspeedtech.com>

The has_otp attribute is enabled in the SBC subclasses for AST2600 to
control the presence of OTP support per SoC type.

Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed_ast2600.c | 2 +-
 hw/misc/aspeed_sbc.c    | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index d12707f0ab..59ffd41a4a 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -261,7 +261,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
 
     object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
 
-    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC);
 
     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index 46a038337c..b56a8b7678 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -273,8 +273,10 @@ static const TypeInfo aspeed_sbc_info = {
 static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
 
     dc->desc = "AST2600 Secure Boot Controller";
+    sc->has_otp = true;
 }
 
 static const TypeInfo aspeed_ast2600_sbc_info = {
-- 
2.43.0



  parent reply	other threads:[~2025-08-12  9:42 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-12  9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
2025-08-12  9:39 ` [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
2025-08-12  9:39 ` [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
2025-08-12  9:40 ` Kane Chen via [this message]
2025-08-12  9:40 ` [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Kane Chen via
2025-08-12  9:40 ` [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Kane Chen via
2025-09-02  5:41   ` [SPAM] " Cédric Le Goater
2025-09-02  5:48     ` Kane Chen
2025-08-12  9:40 ` [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Kane Chen via
2025-09-02  5:41   ` [SPAM] " Cédric Le Goater
2025-09-02  5:44 ` [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Cédric Le Goater
2025-09-02  6:05   ` Kane Chen

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