* [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
@ 2025-08-12 9:39 ` Kane Chen via
2025-08-12 9:39 ` [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
` (9 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:39 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a dedicated
AddressSpace, allowing other device models (e.g., SBC) to issue
transactions as if accessing a memory-mapped region.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/nvram/aspeed_otp.h | 33 ++++++++++++
hw/nvram/aspeed_otp.c | 99 +++++++++++++++++++++++++++++++++++
hw/nvram/meson.build | 4 ++
3 files changed, 136 insertions(+)
create mode 100644 include/hw/nvram/aspeed_otp.h
create mode 100644 hw/nvram/aspeed_otp.c
diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h
new file mode 100644
index 0000000000..3752353860
--- /dev/null
+++ b/include/hw/nvram/aspeed_otp.h
@@ -0,0 +1,33 @@
+/*
+ * ASPEED OTP (One-Time Programmable) memory
+ *
+ * Copyright (C) 2025 Aspeed
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_OTP_H
+#define ASPEED_OTP_H
+
+#include "system/memory.h"
+#include "hw/block/block.h"
+#include "system/address-spaces.h"
+
+#define TYPE_ASPEED_OTP "aspeed-otp"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
+
+typedef struct AspeedOTPState {
+ DeviceState parent_obj;
+
+ BlockBackend *blk;
+
+ uint64_t size;
+
+ AddressSpace as;
+
+ MemoryRegion mmio;
+
+ uint8_t *storage;
+} AspeedOTPState;
+
+#endif /* ASPEED_OTP_H */
diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
new file mode 100644
index 0000000000..e5b7ca9676
--- /dev/null
+++ b/hw/nvram/aspeed_otp.c
@@ -0,0 +1,99 @@
+/*
+ * ASPEED OTP (One-Time Programmable) memory
+ *
+ * Copyright (C) 2025 Aspeed
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "system/block-backend.h"
+#include "hw/qdev-properties.h"
+#include "hw/nvram/aspeed_otp.h"
+
+static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedOTPState *s = opaque;
+ uint64_t val = 0;
+
+ memcpy(&val, s->storage + offset, size);
+
+ return val;
+}
+
+static void aspeed_otp_write(void *opaque, hwaddr otp_addr,
+ uint64_t val, unsigned size)
+{
+ AspeedOTPState *s = opaque;
+
+ memcpy(s->storage + otp_addr, &val, size);
+}
+
+static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
+{
+ uint32_t *p;
+ int i, num;
+
+ num = s->size / sizeof(uint32_t);
+ p = (uint32_t *)s->storage;
+ for (i = 0; i < num; i++) {
+ p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
+ }
+
+ return true;
+}
+
+static const MemoryRegionOps aspeed_otp_ops = {
+ .read = aspeed_otp_read,
+ .write = aspeed_otp_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+};
+
+static void aspeed_otp_realize(DeviceState *dev, Error **errp)
+{
+ AspeedOTPState *s = ASPEED_OTP(dev);
+
+ if (s->size == 0) {
+ error_setg(errp, "aspeed.otp: 'size' property must be set");
+ return;
+ }
+
+ s->storage = blk_blockalign(s->blk, s->size);
+
+ if (!aspeed_otp_init_storage(s, errp)) {
+ return;
+ }
+
+ memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
+ s, "aspeed.otp", s->size);
+ address_space_init(&s->as, &s->mmio, NULL);
+}
+
+static const Property aspeed_otp_properties[] = {
+ DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
+};
+
+static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = aspeed_otp_realize;
+ device_class_set_props(dc, aspeed_otp_properties);
+}
+
+static const TypeInfo aspeed_otp_info = {
+ .name = TYPE_ASPEED_OTP,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AspeedOTPState),
+ .class_init = aspeed_otp_class_init,
+};
+
+static void aspeed_otp_register_types(void)
+{
+ type_register_static(&aspeed_otp_info);
+}
+
+type_init(aspeed_otp_register_types)
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 10f3639db6..b66f23605b 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
+
+system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ 'aspeed_otp.c',
+ ))
\ No newline at end of file
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
2025-08-12 9:39 ` [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
@ 2025-08-12 9:39 ` Kane Chen via
2025-08-12 9:40 ` [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Kane Chen via
` (8 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:39 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming
flows.
The following OTP commands are supported:
- READ: reads a 32-bit word from OTP memory into internal registers
- PROG: programs a 32-bit word value to the specified OTP address
Trace events are added to observe read/program operations and command
handling flow.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/misc/aspeed_sbc.h | 5 ++
hw/misc/aspeed_sbc.c | 111 +++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 5 ++
3 files changed, 121 insertions(+)
diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
index 405e6782b9..0c2746d392 100644
--- a/include/hw/misc/aspeed_sbc.h
+++ b/include/hw/misc/aspeed_sbc.h
@@ -10,6 +10,7 @@
#define ASPEED_SBC_H
#include "hw/sysbus.h"
+#include "hw/nvram/aspeed_otp.h"
#define TYPE_ASPEED_SBC "aspeed.sbc"
#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
@@ -36,10 +37,14 @@ struct AspeedSBCState {
MemoryRegion iomem;
uint32_t regs[ASPEED_SBC_NR_REGS];
+
+ AspeedOTPState otp;
};
struct AspeedSBCClass {
SysBusDeviceClass parent_class;
+
+ bool has_otp;
};
#endif /* ASPEED_SBC_H */
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index a7d101ba71..46a038337c 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -15,9 +15,13 @@
#include "hw/misc/aspeed_sbc.h"
#include "qapi/error.h"
#include "migration/vmstate.h"
+#include "trace.h"
#define R_PROT (0x000 / 4)
+#define R_CMD (0x004 / 4)
+#define R_ADDR (0x010 / 4)
#define R_STATUS (0x014 / 4)
+#define R_CAMP1 (0x020 / 4)
#define R_QSR (0x040 / 4)
/* R_STATUS */
@@ -41,6 +45,11 @@
#define QSR_RSA_MASK (0x3 << 12)
#define QSR_HASH_MASK (0x3 << 10)
+#define OTP_MEMORY_SIZE 0x4000
+/* OTP command */
+#define SBC_OTP_CMD_READ 0x23b1e361
+#define SBC_OTP_CMD_PROG 0x23b1e364
+
static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
{
AspeedSBCState *s = ASPEED_SBC(opaque);
@@ -57,6 +66,84 @@ static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
return s->regs[addr];
}
+static bool aspeed_sbc_otp_read(AspeedSBCState *s,
+ uint32_t otp_addr)
+{
+ MemTxResult ret;
+ AspeedOTPState *otp = &s->otp;
+ uint32_t value, otp_offset;
+
+ otp_offset = otp_addr << 2;
+ ret = address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED,
+ &value, sizeof(value));
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to read OTP memory, addr = %x\n",
+ otp_addr);
+ return false;
+ }
+ s->regs[R_CAMP1] = value;
+ trace_aspeed_sbc_otp_read(otp_addr, value);
+
+ return true;
+}
+
+static bool aspeed_sbc_otp_prog(AspeedSBCState *s,
+ uint32_t otp_addr)
+{
+ MemTxResult ret;
+ AspeedOTPState *otp = &s->otp;
+ uint32_t value = s->regs[R_CAMP1];
+
+ ret = address_space_write(&otp->as, otp_addr, MEMTXATTRS_UNSPECIFIED,
+ &value, sizeof(value));
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to write OTP memory, addr = %x\n",
+ otp_addr);
+ return false;
+ }
+
+ trace_aspeed_sbc_otp_prog(otp_addr, value);
+
+ return true;
+}
+
+static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd)
+{
+ AspeedSBCState *s = ASPEED_SBC(opaque);
+ AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(opaque);
+ bool ret = false;
+ uint32_t otp_addr;
+
+ if (!sc->has_otp) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: OTP memory is not supported\n",
+ __func__);
+ return;
+ }
+
+ s->regs[R_STATUS] &= ~(OTP_MEM_IDLE | OTP_IDLE);
+ otp_addr = s->regs[R_ADDR];
+
+ switch (cmd) {
+ case SBC_OTP_CMD_READ:
+ ret = aspeed_sbc_otp_read(s, otp_addr);
+ break;
+ case SBC_OTP_CMD_PROG:
+ ret = aspeed_sbc_otp_prog(s, otp_addr);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unknown command 0x%x\n",
+ __func__, cmd);
+ break;
+ }
+
+ trace_aspeed_sbc_handle_cmd(cmd, otp_addr, ret);
+ s->regs[R_STATUS] |= (OTP_MEM_IDLE | OTP_IDLE);
+}
+
static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
unsigned int size)
{
@@ -78,6 +165,9 @@ static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
"%s: write to read only register 0x%" HWADDR_PRIx "\n",
__func__, addr << 2);
return;
+ case R_CMD:
+ aspeed_sbc_handle_command(opaque, data);
+ return;
default:
break;
}
@@ -115,10 +205,30 @@ static void aspeed_sbc_reset(DeviceState *dev)
s->regs[R_QSR] = s->signing_settings;
}
+static void aspeed_sbc_instance_init(Object *obj)
+{
+ AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(obj);
+ AspeedSBCState *s = ASPEED_SBC(obj);
+
+ if (sc->has_otp) {
+ object_initialize_child(OBJECT(s), "otp", &s->otp,
+ TYPE_ASPEED_OTP);
+ }
+}
+
static void aspeed_sbc_realize(DeviceState *dev, Error **errp)
{
AspeedSBCState *s = ASPEED_SBC(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(dev);
+
+ if (sc->has_otp) {
+ object_property_set_int(OBJECT(&s->otp), "size",
+ OTP_MEMORY_SIZE, &error_abort);
+ if (!qdev_realize(DEVICE(&s->otp), NULL, errp)) {
+ return;
+ }
+ }
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s,
TYPE_ASPEED_SBC, 0x1000);
@@ -155,6 +265,7 @@ static const TypeInfo aspeed_sbc_info = {
.name = TYPE_ASPEED_SBC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSBCState),
+ .instance_init = aspeed_sbc_instance_init,
.class_init = aspeed_sbc_class_init,
.class_size = sizeof(AspeedSBCClass)
};
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index e3f64c0ff6..9e05b82f37 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -90,6 +90,11 @@ slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x"
slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
+# aspeed_sbc.c
+aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling command 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d"
+aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr 0x%" PRIx32 " value 0x%" PRIx32
+aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr 0x%" PRIx32 " value 0x%" PRIx32
+
# aspeed_scu.c
aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
2025-08-12 9:39 ` [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
2025-08-12 9:39 ` [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-08-12 9:40 ` [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Kane Chen via
` (7 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
The has_otp attribute is enabled in the SBC subclasses for AST2600 to
control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index d12707f0ab..59ffd41a4a 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -261,7 +261,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
- object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+ object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC);
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index 46a038337c..b56a8b7678 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -273,8 +273,10 @@ static const TypeInfo aspeed_sbc_info = {
static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
dc->desc = "AST2600 Secure Boot Controller";
+ sc->has_otp = true;
}
static const TypeInfo aspeed_ast2600_sbc_info = {
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (2 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-08-12 9:40 ` [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Kane Chen via
` (6 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
This patch introduces a 'drive' property to the Aspeed OTP device,
allowing it to be backed by a block device. Users can now preload
OTP data via QEMU CLI using a block backend.
Example usage:
./qemu-system-arm \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
-global aspeed-otp.drive=otp \
...
If the drive is provided, its content will be loaded as the initial OTP
state. Otherwise, an internal memory buffer will be used.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/nvram/aspeed_otp.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
index e5b7ca9676..abb3731823 100644
--- a/hw/nvram/aspeed_otp.c
+++ b/hw/nvram/aspeed_otp.c
@@ -35,13 +35,25 @@ static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
{
uint32_t *p;
int i, num;
+ uint64_t perm;
+ if (s->blk) {
+ perm = BLK_PERM_CONSISTENT_READ |
+ (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
+ if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
+ return false;
+ }
+ if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
+ error_setg(errp, "Failed to read the initial flash content");
+ return false;
+ }
+ } else {
num = s->size / sizeof(uint32_t);
p = (uint32_t *)s->storage;
for (i = 0; i < num; i++) {
p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
}
-
+ }
return true;
}
@@ -75,6 +87,7 @@ static void aspeed_otp_realize(DeviceState *dev, Error **errp)
static const Property aspeed_otp_properties[] = {
DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
+ DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk),
};
static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (3 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:32 ` [SPAM] " Cédric Le Goater
2025-08-12 9:40 ` [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Kane Chen via
` (5 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Implement correct OTP programming behavior for Aspeed OTP:
- Support read-modify-write flow with one-way bit programming:
* prog_bit uses 0s as the "to-be-programmed" mask.
* Even-indexed words: 0->1, odd-indexed words: 1->0.
* Reject non-programmable requests and log conflicts.
- Enable unaligned accesses in MemoryRegionOps.
Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the
backing store, upper-layer accesses may be unaligned to block
boundaries.
This matches the irreversible, word-parity-dependent programming rules
of Aspeed SoCs and exposes changes via QEMU trace events.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
hw/nvram/aspeed_otp.c | 80 ++++++++++++++++++++++++++++++++++++++++++-
hw/nvram/trace-events | 5 +++
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
index abb3731823..66b2bfea28 100644
--- a/hw/nvram/aspeed_otp.c
+++ b/hw/nvram/aspeed_otp.c
@@ -12,6 +12,7 @@
#include "system/block-backend.h"
#include "hw/qdev-properties.h"
#include "hw/nvram/aspeed_otp.h"
+#include "hw/nvram/trace.h"
static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
{
@@ -23,12 +24,87 @@ static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
return val;
}
+static bool valid_program_data(uint32_t otp_addr,
+ uint32_t value, uint32_t prog_bit)
+{
+ uint32_t programmed_bits, has_programmable_bits;
+ bool is_odd = otp_addr & 1;
+
+ /*
+ * prog_bit uses 0s to indicate target bits to program:
+ * - if OTP word is even-indexed, programmed bits flip 0->1
+ * - if odd, bits flip 1->0
+ * Bit programming is one-way only and irreversible.
+ */
+ if (is_odd) {
+ programmed_bits = ~value & prog_bit;
+ } else {
+ programmed_bits = value & (~prog_bit);
+ }
+
+ /* If any bit can be programmed, accept the request */
+ has_programmable_bits = value ^ (~prog_bit);
+
+ if (programmed_bits) {
+ trace_aspeed_otp_prog_conflict(otp_addr, programmed_bits);
+ for (int i = 0; i < 32; ++i) {
+ if (programmed_bits & (1U << i)) {
+ trace_aspeed_otp_prog_bit(i);
+ }
+ }
+ }
+
+ return has_programmable_bits != 0;
+}
+
+static bool program_otpmem_data(void *opaque, uint32_t otp_addr,
+ uint32_t prog_bit, uint32_t *value)
+{
+ AspeedOTPState *s = opaque;
+ bool is_odd = otp_addr & 1;
+ uint32_t otp_offset = otp_addr << 2;
+
+ memcpy(value, s->storage + otp_offset, sizeof(uint32_t));
+
+ if (!valid_program_data(otp_addr, *value, prog_bit)) {
+ return false;
+ }
+
+ if (is_odd) {
+ *value &= ~prog_bit;
+ } else {
+ *value |= ~prog_bit;
+ }
+
+ return true;
+}
+
static void aspeed_otp_write(void *opaque, hwaddr otp_addr,
uint64_t val, unsigned size)
{
AspeedOTPState *s = opaque;
+ uint32_t otp_offset, value;
- memcpy(s->storage + otp_addr, &val, size);
+ if (!program_otpmem_data(s, otp_addr, val, &value)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Failed to program data, value = %x, bit = %lx\n",
+ __func__, value, val);
+ return;
+ }
+
+ otp_offset = otp_addr << 2;
+ memcpy(s->storage + otp_offset, &value, size);
+
+ if (s->blk) {
+ if (blk_pwrite(s->blk, otp_offset, size, &value, 0) < 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Failed to write %x to %x\n",
+ __func__, value, otp_offset);
+
+ return;
+ }
+ }
+ trace_aspeed_otp_prog(otp_offset, val, value);
}
static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
@@ -63,6 +139,8 @@ static const MemoryRegionOps aspeed_otp_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
+ .valid.unaligned = true,
+ .impl.unaligned = true
};
static void aspeed_otp_realize(DeviceState *dev, Error **errp)
diff --git a/hw/nvram/trace-events b/hw/nvram/trace-events
index 5e33b24d47..7084bf70d3 100644
--- a/hw/nvram/trace-events
+++ b/hw/nvram/trace-events
@@ -1,5 +1,10 @@
# See docs/devel/tracing.rst for syntax documentation.
+# aspeed_otp.c
+aspeed_otp_prog(uint32_t addr, uint32_t prog_value, uint32_t value) "OTP Memory program: addr 0x%" PRIx32 " prog_value 0x%" PRIx32 " value 0x%" PRIx32
+aspeed_otp_prog_conflict(uint32_t addr, uint32_t bits) "Conflict at addr=0x%x, bits=0x%08x"
+aspeed_otp_prog_bit(int bit) "Programmed bit %d"
+
# ds1225y.c
nvram_read(uint32_t addr, uint32_t ret) "read addr %d: 0x%02x"
nvram_write(uint32_t addr, uint32_t old, uint32_t val) "write addr %d: 0x%02x -> 0x%02x"
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
2025-08-12 9:40 ` [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Kane Chen via
@ 2025-09-02 5:32 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:32 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Implement correct OTP programming behavior for Aspeed OTP:
> - Support read-modify-write flow with one-way bit programming:
> * prog_bit uses 0s as the "to-be-programmed" mask.
> * Even-indexed words: 0->1, odd-indexed words: 1->0.
> * Reject non-programmable requests and log conflicts.
> - Enable unaligned accesses in MemoryRegionOps.
> Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the
> backing store, upper-layer accesses may be unaligned to block
> boundaries.
>
> This matches the irreversible, word-parity-dependent programming rules
> of Aspeed SoCs and exposes changes via QEMU trace events.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/nvram/aspeed_otp.c | 80 ++++++++++++++++++++++++++++++++++++++++++-
> hw/nvram/trace-events | 5 +++
> 2 files changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
> index abb3731823..66b2bfea28 100644
> --- a/hw/nvram/aspeed_otp.c
> +++ b/hw/nvram/aspeed_otp.c
> @@ -12,6 +12,7 @@
> #include "system/block-backend.h"
> #include "hw/qdev-properties.h"
> #include "hw/nvram/aspeed_otp.h"
> +#include "hw/nvram/trace.h"
>
> static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
> {
> @@ -23,12 +24,87 @@ static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
> return val;
> }
>
> +static bool valid_program_data(uint32_t otp_addr,
> + uint32_t value, uint32_t prog_bit)
> +{
> + uint32_t programmed_bits, has_programmable_bits;
> + bool is_odd = otp_addr & 1;
> +
> + /*
> + * prog_bit uses 0s to indicate target bits to program:
> + * - if OTP word is even-indexed, programmed bits flip 0->1
> + * - if odd, bits flip 1->0
> + * Bit programming is one-way only and irreversible.
> + */
> + if (is_odd) {
> + programmed_bits = ~value & prog_bit;
> + } else {
> + programmed_bits = value & (~prog_bit);
> + }
> +
> + /* If any bit can be programmed, accept the request */
> + has_programmable_bits = value ^ (~prog_bit);
> +
> + if (programmed_bits) {
> + trace_aspeed_otp_prog_conflict(otp_addr, programmed_bits);
> + for (int i = 0; i < 32; ++i) {
> + if (programmed_bits & (1U << i)) {
> + trace_aspeed_otp_prog_bit(i);
> + }
> + }
> + }
> +
> + return has_programmable_bits != 0;
> +}
> +
> +static bool program_otpmem_data(void *opaque, uint32_t otp_addr,
> + uint32_t prog_bit, uint32_t *value)
> +{
> + AspeedOTPState *s = opaque;
> + bool is_odd = otp_addr & 1;
> + uint32_t otp_offset = otp_addr << 2;
> +
> + memcpy(value, s->storage + otp_offset, sizeof(uint32_t));
> +
> + if (!valid_program_data(otp_addr, *value, prog_bit)) {
> + return false;
> + }
> +
> + if (is_odd) {
> + *value &= ~prog_bit;
> + } else {
> + *value |= ~prog_bit;
> + }
> +
> + return true;
> +}
> +
> static void aspeed_otp_write(void *opaque, hwaddr otp_addr,
> uint64_t val, unsigned size)
> {
> AspeedOTPState *s = opaque;
> + uint32_t otp_offset, value;
>
> - memcpy(s->storage + otp_addr, &val, size);
> + if (!program_otpmem_data(s, otp_addr, val, &value)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Failed to program data, value = %x, bit = %lx\n",
> + __func__, value, val);
> + return;
> + }
> +
> + otp_offset = otp_addr << 2;
> + memcpy(s->storage + otp_offset, &value, size);
> +
> + if (s->blk) {
> + if (blk_pwrite(s->blk, otp_offset, size, &value, 0) < 0) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Failed to write %x to %x\n",
> + __func__, value, otp_offset);
> +
> + return;
> + }
> + }
> + trace_aspeed_otp_prog(otp_offset, val, value);
> }
>
> static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
> @@ -63,6 +139,8 @@ static const MemoryRegionOps aspeed_otp_ops = {
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
> + .valid.unaligned = true,
> + .impl.unaligned = true
> };
>
> static void aspeed_otp_realize(DeviceState *dev, Error **errp)
> diff --git a/hw/nvram/trace-events b/hw/nvram/trace-events
> index 5e33b24d47..7084bf70d3 100644
> --- a/hw/nvram/trace-events
> +++ b/hw/nvram/trace-events
> @@ -1,5 +1,10 @@
> # See docs/devel/tracing.rst for syntax documentation.
>
> +# aspeed_otp.c
> +aspeed_otp_prog(uint32_t addr, uint32_t prog_value, uint32_t value) "OTP Memory program: addr 0x%" PRIx32 " prog_value 0x%" PRIx32 " value 0x%" PRIx32
> +aspeed_otp_prog_conflict(uint32_t addr, uint32_t bits) "Conflict at addr=0x%x, bits=0x%08x"
> +aspeed_otp_prog_bit(int bit) "Programmed bit %d"
> +
> # ds1225y.c
> nvram_read(uint32_t addr, uint32_t ret) "read addr %d: 0x%02x"
> nvram_write(uint32_t addr, uint32_t old, uint32_t val) "write addr %d: 0x%02x -> 0x%02x"
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (4 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:32 ` [SPAM] " Cédric Le Goater
2025-08-12 9:40 ` [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Kane Chen via
` (4 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
The has_otp attribute is enabled in the SBC subclasses for AST1030 to
control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_sbc.h | 1 +
hw/arm/aspeed_ast10x0.c | 2 +-
hw/misc/aspeed_sbc.c | 16 ++++++++++++++++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
index 0c2746d392..7d640a022e 100644
--- a/include/hw/misc/aspeed_sbc.h
+++ b/include/hw/misc/aspeed_sbc.h
@@ -14,6 +14,7 @@
#define TYPE_ASPEED_SBC "aspeed.sbc"
#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
+#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0"
OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
#define ASPEED_SBC_NR_REGS (0x93c >> 2)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index e6e1ee63c1..c446e70b24 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
- object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+ object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC);
for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index b56a8b7678..052c70fd42 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -285,9 +285,25 @@ static const TypeInfo aspeed_ast2600_sbc_info = {
.class_init = aspeed_ast2600_sbc_class_init,
};
+static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
+
+ dc->desc = "AST10X0 Secure Boot Controller";
+ sc->has_otp = true;
+}
+
+static const TypeInfo aspeed_ast10x0_sbc_info = {
+ .name = TYPE_ASPEED_AST10X0_SBC,
+ .parent = TYPE_ASPEED_SBC,
+ .class_init = aspeed_ast10x0_sbc_class_init,
+};
+
static void aspeed_sbc_register_types(void)
{
type_register_static(&aspeed_ast2600_sbc_info);
+ type_register_static(&aspeed_ast10x0_sbc_info);
type_register_static(&aspeed_sbc_info);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
2025-08-12 9:40 ` [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Kane Chen via
@ 2025-09-02 5:32 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:32 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> The has_otp attribute is enabled in the SBC subclasses for AST1030 to
> control the presence of OTP support per SoC type.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/misc/aspeed_sbc.h | 1 +
> hw/arm/aspeed_ast10x0.c | 2 +-
> hw/misc/aspeed_sbc.c | 16 ++++++++++++++++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
> index 0c2746d392..7d640a022e 100644
> --- a/include/hw/misc/aspeed_sbc.h
> +++ b/include/hw/misc/aspeed_sbc.h
> @@ -14,6 +14,7 @@
>
> #define TYPE_ASPEED_SBC "aspeed.sbc"
> #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
> +#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0"
> OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
>
> #define ASPEED_SBC_NR_REGS (0x93c >> 2)
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index e6e1ee63c1..c446e70b24 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
>
> object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
>
> - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
> + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC);
>
> for (i = 0; i < sc->wdts_num; i++) {
> snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
> diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
> index b56a8b7678..052c70fd42 100644
> --- a/hw/misc/aspeed_sbc.c
> +++ b/hw/misc/aspeed_sbc.c
> @@ -285,9 +285,25 @@ static const TypeInfo aspeed_ast2600_sbc_info = {
> .class_init = aspeed_ast2600_sbc_class_init,
> };
>
> +static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
> +
> + dc->desc = "AST10X0 Secure Boot Controller";
> + sc->has_otp = true;
> +}
> +
> +static const TypeInfo aspeed_ast10x0_sbc_info = {
> + .name = TYPE_ASPEED_AST10X0_SBC,
> + .parent = TYPE_ASPEED_SBC,
> + .class_init = aspeed_ast10x0_sbc_class_init,
> +};
> +
> static void aspeed_sbc_register_types(void)
> {
> type_register_static(&aspeed_ast2600_sbc_info);
> + type_register_static(&aspeed_ast10x0_sbc_info);
> type_register_static(&aspeed_sbc_info);
> }
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (5 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:32 ` [SPAM] " Cédric Le Goater
2025-08-12 9:40 ` [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Kane Chen via
` (3 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
The OTP space contains three types of entries: data, conf, and strap.
Data entries consist of two DWORDs, while the other types contain
only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to
store the second DWORD when reading from the OTP data region.
With this enhancement, OTP reads now correctly return both DWORDs for
data entries via the CAMP registers, along with improved address
validation and error handling.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
hw/misc/aspeed_sbc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index 052c70fd42..787e2d0489 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -22,6 +22,7 @@
#define R_ADDR (0x010 / 4)
#define R_STATUS (0x014 / 4)
#define R_CAMP1 (0x020 / 4)
+#define R_CAMP2 (0x024 / 4)
#define R_QSR (0x040 / 4)
/* R_STATUS */
@@ -50,6 +51,8 @@
#define SBC_OTP_CMD_READ 0x23b1e361
#define SBC_OTP_CMD_PROG 0x23b1e364
+#define OTP_DATA_DWORD_COUNT (0x800)
+#define OTP_TOTAL_DWORD_COUNT (0x1000)
static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
{
AspeedSBCState *s = ASPEED_SBC(opaque);
@@ -72,6 +75,16 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
MemTxResult ret;
AspeedOTPState *otp = &s->otp;
uint32_t value, otp_offset;
+ bool is_data = false;
+
+ if (otp_addr < OTP_DATA_DWORD_COUNT) {
+ is_data = true;
+ } else if (otp_addr >= OTP_TOTAL_DWORD_COUNT) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Invalid OTP addr 0x%x\n",
+ otp_addr);
+ return false;
+ }
otp_offset = otp_addr << 2;
ret = address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED,
@@ -85,6 +98,20 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
s->regs[R_CAMP1] = value;
trace_aspeed_sbc_otp_read(otp_addr, value);
+ if (is_data) {
+ ret = address_space_read(&otp->as, otp_offset + 4,
+ MEMTXATTRS_UNSPECIFIED,
+ &value, sizeof(value));
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to read OTP memory, addr = %x\n",
+ otp_addr);
+ return false;
+ }
+ s->regs[R_CAMP2] = value;
+ trace_aspeed_sbc_otp_read(otp_addr + 1, value);
+ }
+
return true;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
2025-08-12 9:40 ` [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Kane Chen via
@ 2025-09-02 5:32 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:32 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> The OTP space contains three types of entries: data, conf, and strap.
> Data entries consist of two DWORDs, while the other types contain
> only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to
> store the second DWORD when reading from the OTP data region.
>
> With this enhancement, OTP reads now correctly return both DWORDs for
> data entries via the CAMP registers, along with improved address
> validation and error handling.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/misc/aspeed_sbc.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
> index 052c70fd42..787e2d0489 100644
> --- a/hw/misc/aspeed_sbc.c
> +++ b/hw/misc/aspeed_sbc.c
> @@ -22,6 +22,7 @@
> #define R_ADDR (0x010 / 4)
> #define R_STATUS (0x014 / 4)
> #define R_CAMP1 (0x020 / 4)
> +#define R_CAMP2 (0x024 / 4)
> #define R_QSR (0x040 / 4)
>
> /* R_STATUS */
> @@ -50,6 +51,8 @@
> #define SBC_OTP_CMD_READ 0x23b1e361
> #define SBC_OTP_CMD_PROG 0x23b1e364
>
> +#define OTP_DATA_DWORD_COUNT (0x800)
> +#define OTP_TOTAL_DWORD_COUNT (0x1000)
> static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
> {
> AspeedSBCState *s = ASPEED_SBC(opaque);
> @@ -72,6 +75,16 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
> MemTxResult ret;
> AspeedOTPState *otp = &s->otp;
> uint32_t value, otp_offset;
> + bool is_data = false;
> +
> + if (otp_addr < OTP_DATA_DWORD_COUNT) {
> + is_data = true;
> + } else if (otp_addr >= OTP_TOTAL_DWORD_COUNT) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Invalid OTP addr 0x%x\n",
> + otp_addr);
> + return false;
> + }
>
> otp_offset = otp_addr << 2;
> ret = address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED,
> @@ -85,6 +98,20 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
> s->regs[R_CAMP1] = value;
> trace_aspeed_sbc_otp_read(otp_addr, value);
>
> + if (is_data) {
> + ret = address_space_read(&otp->as, otp_offset + 4,
> + MEMTXATTRS_UNSPECIFIED,
> + &value, sizeof(value));
> + if (ret != MEMTX_OK) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to read OTP memory, addr = %x\n",
> + otp_addr);
> + return false;
> + }
> + s->regs[R_CAMP2] = value;
> + trace_aspeed_sbc_otp_read(otp_addr + 1, value);
> + }
> +
> return true;
> }
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (6 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:32 ` [SPAM] " Cédric Le Goater
2025-08-12 9:40 ` [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Kane Chen via
` (2 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Extend OTP command handling to recognize specific voltage mode register
addresses and emulate the expected hardware behavior. Without this
change, legitimate voltage mode change requests would be incorrectly
reported as "Unknown command" and logged as an error.
This implementation does not perform actual mode changes, but ensures
that valid requests are accepted and ignored as per hardware behavior.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
hw/misc/aspeed_sbc.c | 41 +++++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 1 +
2 files changed, 42 insertions(+)
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index 787e2d0489..2fc5db749d 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -49,10 +49,17 @@
#define OTP_MEMORY_SIZE 0x4000
/* OTP command */
#define SBC_OTP_CMD_READ 0x23b1e361
+#define SBC_OTP_CMD_WRITE 0x23b1e362
#define SBC_OTP_CMD_PROG 0x23b1e364
#define OTP_DATA_DWORD_COUNT (0x800)
#define OTP_TOTAL_DWORD_COUNT (0x1000)
+
+/* Voltage mode */
+#define MODE_REGISTER (0x1000)
+#define MODE_REGISTER_A (0x3000)
+#define MODE_REGISTER_B (0x5000)
+
static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
{
AspeedSBCState *s = ASPEED_SBC(opaque);
@@ -115,6 +122,37 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
return true;
}
+static bool mode_handler(uint32_t otp_addr)
+{
+ switch (otp_addr) {
+ case MODE_REGISTER:
+ case MODE_REGISTER_A:
+ case MODE_REGISTER_B:
+ /* HW behavior, do nothing here */
+ return true;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Unsupported address 0x%x\n",
+ otp_addr);
+ return false;
+ }
+}
+
+static bool aspeed_sbc_otp_write(AspeedSBCState *s,
+ uint32_t otp_addr)
+{
+ if (otp_addr == 0) {
+ trace_aspeed_sbc_ignore_cmd(otp_addr);
+ return true;
+ } else {
+ if (mode_handler(otp_addr) == false) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
static bool aspeed_sbc_otp_prog(AspeedSBCState *s,
uint32_t otp_addr)
{
@@ -157,6 +195,9 @@ static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd)
case SBC_OTP_CMD_READ:
ret = aspeed_sbc_otp_read(s, otp_addr);
break;
+ case SBC_OTP_CMD_WRITE:
+ ret = aspeed_sbc_otp_write(s, otp_addr);
+ break;
case SBC_OTP_CMD_PROG:
ret = aspeed_sbc_otp_prog(s, otp_addr);
break;
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 9e05b82f37..eeb9243898 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -91,6 +91,7 @@ slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
# aspeed_sbc.c
+aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%" PRIx32
aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling command 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d"
aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr 0x%" PRIx32 " value 0x%" PRIx32
aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr 0x%" PRIx32 " value 0x%" PRIx32
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers
2025-08-12 9:40 ` [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Kane Chen via
@ 2025-09-02 5:32 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:32 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Extend OTP command handling to recognize specific voltage mode register
> addresses and emulate the expected hardware behavior. Without this
> change, legitimate voltage mode change requests would be incorrectly
> reported as "Unknown command" and logged as an error.
>
> This implementation does not perform actual mode changes, but ensures
> that valid requests are accepted and ignored as per hardware behavior.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/misc/aspeed_sbc.c | 41 +++++++++++++++++++++++++++++++++++++++++
> hw/misc/trace-events | 1 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
> index 787e2d0489..2fc5db749d 100644
> --- a/hw/misc/aspeed_sbc.c
> +++ b/hw/misc/aspeed_sbc.c
> @@ -49,10 +49,17 @@
> #define OTP_MEMORY_SIZE 0x4000
> /* OTP command */
> #define SBC_OTP_CMD_READ 0x23b1e361
> +#define SBC_OTP_CMD_WRITE 0x23b1e362
> #define SBC_OTP_CMD_PROG 0x23b1e364
>
> #define OTP_DATA_DWORD_COUNT (0x800)
> #define OTP_TOTAL_DWORD_COUNT (0x1000)
> +
> +/* Voltage mode */
> +#define MODE_REGISTER (0x1000)
> +#define MODE_REGISTER_A (0x3000)
> +#define MODE_REGISTER_B (0x5000)
> +
> static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
> {
> AspeedSBCState *s = ASPEED_SBC(opaque);
> @@ -115,6 +122,37 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
> return true;
> }
>
> +static bool mode_handler(uint32_t otp_addr)
> +{
> + switch (otp_addr) {
> + case MODE_REGISTER:
> + case MODE_REGISTER_A:
> + case MODE_REGISTER_B:
> + /* HW behavior, do nothing here */
> + return true;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Unsupported address 0x%x\n",
> + otp_addr);
> + return false;
> + }
> +}
> +
> +static bool aspeed_sbc_otp_write(AspeedSBCState *s,
> + uint32_t otp_addr)
> +{
> + if (otp_addr == 0) {
> + trace_aspeed_sbc_ignore_cmd(otp_addr);
> + return true;
> + } else {
> + if (mode_handler(otp_addr) == false) {
> + return false;
> + }
> + }
> +
> + return true;
> +}
> +
> static bool aspeed_sbc_otp_prog(AspeedSBCState *s,
> uint32_t otp_addr)
> {
> @@ -157,6 +195,9 @@ static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd)
> case SBC_OTP_CMD_READ:
> ret = aspeed_sbc_otp_read(s, otp_addr);
> break;
> + case SBC_OTP_CMD_WRITE:
> + ret = aspeed_sbc_otp_write(s, otp_addr);
> + break;
> case SBC_OTP_CMD_PROG:
> ret = aspeed_sbc_otp_prog(s, otp_addr);
> break;
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index 9e05b82f37..eeb9243898 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -91,6 +91,7 @@ slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
> slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
>
> # aspeed_sbc.c
> +aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%" PRIx32
> aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling command 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d"
> aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr 0x%" PRIx32 " value 0x%" PRIx32
> aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr 0x%" PRIx32 " value 0x%" PRIx32
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (7 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:41 ` [SPAM] " Cédric Le Goater
2025-08-12 9:40 ` [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Kane Chen via
2025-09-02 5:44 ` [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Cédric Le Goater
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
On boot, the SoC firmware reads data from the OTP region to obtain the
chip ID and default settings. This change adds test cases to verify
that the firmware can boot correctly with a pre-configured OTP image.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
tests/functional/meson.build | 2 +
tests/functional/test_arm_aspeed_otp.py | 55 +++++++++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 tests/functional/test_arm_aspeed_otp.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 311c6f1806..c731b779dd 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -34,6 +34,7 @@ test_timeouts = {
'arm_aspeed_bletchley' : 480,
'arm_aspeed_catalina' : 480,
'arm_aspeed_gb200nvl_bmc' : 480,
+ 'arm_aspeed_otp': 1200,
'arm_aspeed_rainier' : 480,
'arm_bpim2u' : 500,
'arm_collie' : 180,
@@ -132,6 +133,7 @@ tests_arm_system_thorough = [
'arm_aspeed_bletchley',
'arm_aspeed_catalina',
'arm_aspeed_gb200nvl_bmc',
+ 'arm_aspeed_otp',
'arm_aspeed_rainier',
'arm_bpim2u',
'arm_canona1100',
diff --git a/tests/functional/test_arm_aspeed_otp.py b/tests/functional/test_arm_aspeed_otp.py
new file mode 100644
index 0000000000..48c7cad3f3
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_otp.py
@@ -0,0 +1,55 @@
+import os
+import time
+import tempfile
+import subprocess
+
+from qemu_test import LinuxKernelTest, Asset
+from aspeed import AspeedTest
+from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingCommands
+
+class AspeedOtpMemoryTest(AspeedTest):
+ # AST2600 SDK image
+ ASSET_SDK_V907_AST2600 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.07/ast2600-default-obmc.tar.gz',
+ 'cb6c08595bcbba1672ce716b068ba4e48eda1ed9abe78a07b30392ba2278feba')
+
+ # AST1030 Zephyr image
+ ASSET_ZEPHYR_3_02 = Asset(
+ 'https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.03.02/ast1030-evb-demo.zip',
+ '1ec83caab3ddd5d09481772801be7210e222cb015ce22ec6fffb8a76956dcd4f')
+
+ def generate_otpmem_image(self):
+ path = self.scratch_file("otpmem.img")
+ pattern = b'\x00\x00\x00\x00\xff\xff\xff\xff' * (16 * 1024 // 8)
+ with open(path, "wb") as f:
+ f.write(pattern)
+ return path
+
+ def test_ast2600_otp_blockdev_device(self):
+ image_path = self.archive_extract(self.ASSET_SDK_V907_AST2600)
+ otp_img = self.generate_otpmem_image()
+ self.vm.set_machine("ast2600-evb")
+ self.vm.set_console()
+ self.vm.add_args(
+ "-blockdev", f"driver=file,filename={otp_img},node-name=otp",
+ "-global", "aspeed-otp.drive=otp",
+ )
+ self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-default", "image-bmc"))
+ self.wait_for_console_pattern("ast2600-default login:")
+
+ def test_ast1030_otp_blockdev_device(self):
+ kernel_name = "ast1030-evb-demo-3/zephyr.elf"
+ kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_02, member=kernel_name)
+ otp_img = self.generate_otpmem_image()
+ self.vm.set_machine("ast1030-evb")
+ self.vm.set_console()
+ self.vm.add_args(
+ "-kernel", kernel_file,
+ "-blockdev", f"driver=file,filename={otp_img},node-name=otp",
+ "-global", "aspeed-otp.drive=otp",
+ )
+ self.vm.launch()
+ self.wait_for_console_pattern("Booting Zephyr OS")
+
+if __name__ == '__main__':
+ AspeedTest.main()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test
2025-08-12 9:40 ` [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Kane Chen via
@ 2025-09-02 5:41 ` Cédric Le Goater
2025-09-02 5:48 ` Kane Chen
0 siblings, 1 reply; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:41 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Thomas Huth
Cc: troy_lee
Hello Kane,
+ Thomas
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> On boot, the SoC firmware reads data from the OTP region to obtain the
> chip ID and default settings. This change adds test cases to verify
> that the firmware can boot correctly with a pre-configured OTP image.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> tests/functional/meson.build | 2 +
> tests/functional/test_arm_aspeed_otp.py | 55 +++++++++++++++++++++++++
> 2 files changed, 57 insertions(+)
> create mode 100644 tests/functional/test_arm_aspeed_otp.py
>
> diff --git a/tests/functional/meson.build b/tests/functional/meson.build
> index 311c6f1806..c731b779dd 100644
> --- a/tests/functional/meson.build
> +++ b/tests/functional/meson.build
> @@ -34,6 +34,7 @@ test_timeouts = {
> 'arm_aspeed_bletchley' : 480,
> 'arm_aspeed_catalina' : 480,
> 'arm_aspeed_gb200nvl_bmc' : 480,
> + 'arm_aspeed_otp': 1200,
> 'arm_aspeed_rainier' : 480,
> 'arm_bpim2u' : 500,
> 'arm_collie' : 180,
> @@ -132,6 +133,7 @@ tests_arm_system_thorough = [
> 'arm_aspeed_bletchley',
> 'arm_aspeed_catalina',
> 'arm_aspeed_gb200nvl_bmc',
> + 'arm_aspeed_otp',
> 'arm_aspeed_rainier',
> 'arm_bpim2u',
> 'arm_canona1100',
> diff --git a/tests/functional/test_arm_aspeed_otp.py b/tests/functional/test_arm_aspeed_otp.py
The tests/functional directory was recently reorganized.
Also, I think I would prefer the new otp test to be part of the
existing test files :
tests/functional/arm/test_aspeed_ast1030.py
tests/functional/arm/test_aspeed_ast2600.py
Something to discuss since test_aspeed_ast2600.py is rather big.
> new file mode 100644
> index 0000000000..48c7cad3f3
> --- /dev/null
> +++ b/tests/functional/test_arm_aspeed_otp.py
> @@ -0,0 +1,55 @@
> +import os
> +import time
> +import tempfile
> +import subprocess
> +
> +from qemu_test import LinuxKernelTest, Asset> +from aspeed import AspeedTest
> +from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingCommands
> +
Please add an extra blank line
> +class AspeedOtpMemoryTest(AspeedTest):
> + # AST2600 SDK image
> + ASSET_SDK_V907_AST2600 = Asset(
> + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.07/ast2600-default-obmc.tar.gz',
> + 'cb6c08595bcbba1672ce716b068ba4e48eda1ed9abe78a07b30392ba2278feba')
Please update first all functional tests with the new SDK v9.07 images.
> +
> + # AST1030 Zephyr image
> + ASSET_ZEPHYR_3_02 = Asset(
> + 'https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.03.02/ast1030-evb-demo.zip',
> + '1ec83caab3ddd5d09481772801be7210e222cb015ce22ec6fffb8a76956dcd4f')
Same for Zephyr images
> +
> + def generate_otpmem_image(self):
> + path = self.scratch_file("otpmem.img")
> + pattern = b'\x00\x00\x00\x00\xff\xff\xff\xff' * (16 * 1024 // 8)
> + with open(path, "wb") as f:
> + f.write(pattern)
> + return path
> +
> + def test_ast2600_otp_blockdev_device(self):
> + image_path = self.archive_extract(self.ASSET_SDK_V907_AST2600)
> + otp_img = self.generate_otpmem_image()
> + self.vm.set_machine("ast2600-evb")
Please move self.vm.set_machine() at the top of the routine.
Thanks,
C.
> + self.vm.set_console()
> + self.vm.add_args(
> + "-blockdev", f"driver=file,filename={otp_img},node-name=otp",
> + "-global", "aspeed-otp.drive=otp",
> + )
> + self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-default", "image-bmc"))
> + self.wait_for_console_pattern("ast2600-default login:")
> +
> + def test_ast1030_otp_blockdev_device(self):
> + kernel_name = "ast1030-evb-demo-3/zephyr.elf"
> + kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_02, member=kernel_name)
> + otp_img = self.generate_otpmem_image()
> + self.vm.set_machine("ast1030-evb")
> + self.vm.set_console()
> + self.vm.add_args(
> + "-kernel", kernel_file,
> + "-blockdev", f"driver=file,filename={otp_img},node-name=otp",
> + "-global", "aspeed-otp.drive=otp",
> + )
> + self.vm.launch()
> + self.wait_for_console_pattern("Booting Zephyr OS")
> +
> +if __name__ == '__main__':
> + AspeedTest.main()
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [SPAM] [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test
2025-09-02 5:41 ` [SPAM] " Cédric Le Goater
@ 2025-09-02 5:48 ` Kane Chen
0 siblings, 0 replies; 20+ messages in thread
From: Kane Chen @ 2025-09-02 5:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Thomas Huth
Cc: Troy Lee
Hi Cédric,
Many thanks for reviewing. I will revise the test script as suggested and resubmit the patch.
Best regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, September 2, 2025 1:41 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>; Thomas Huth <thuth@redhat.com>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [SPAM] [PATCH v5 09/10] tests/function/aspeed: Add OTP
> functional test
>
> Hello Kane,
>
> + Thomas
>
> On 8/12/25 11:40, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > On boot, the SoC firmware reads data from the OTP region to obtain the
> > chip ID and default settings. This change adds test cases to verify
> > that the firmware can boot correctly with a pre-configured OTP image.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > tests/functional/meson.build | 2 +
> > tests/functional/test_arm_aspeed_otp.py | 55
> +++++++++++++++++++++++++
> > 2 files changed, 57 insertions(+)
> > create mode 100644 tests/functional/test_arm_aspeed_otp.py
> >
> > diff --git a/tests/functional/meson.build
> > b/tests/functional/meson.build index 311c6f1806..c731b779dd 100644
> > --- a/tests/functional/meson.build
> > +++ b/tests/functional/meson.build
> > @@ -34,6 +34,7 @@ test_timeouts = {
> > 'arm_aspeed_bletchley' : 480,
> > 'arm_aspeed_catalina' : 480,
> > 'arm_aspeed_gb200nvl_bmc' : 480,
> > + 'arm_aspeed_otp': 1200,
> > 'arm_aspeed_rainier' : 480,
> > 'arm_bpim2u' : 500,
> > 'arm_collie' : 180,
> > @@ -132,6 +133,7 @@ tests_arm_system_thorough = [
> > 'arm_aspeed_bletchley',
> > 'arm_aspeed_catalina',
> > 'arm_aspeed_gb200nvl_bmc',
> > + 'arm_aspeed_otp',
> > 'arm_aspeed_rainier',
> > 'arm_bpim2u',
> > 'arm_canona1100',
> > diff --git a/tests/functional/test_arm_aspeed_otp.py
> > b/tests/functional/test_arm_aspeed_otp.py
>
> The tests/functional directory was recently reorganized.
>
> Also, I think I would prefer the new otp test to be part of the existing test files :
>
> tests/functional/arm/test_aspeed_ast1030.py
> tests/functional/arm/test_aspeed_ast2600.py
>
> Something to discuss since test_aspeed_ast2600.py is rather big.
>
>
> > new file mode 100644
> > index 0000000000..48c7cad3f3
> > --- /dev/null
> > +++ b/tests/functional/test_arm_aspeed_otp.py
> > @@ -0,0 +1,55 @@
> > +import os
> > +import time
> > +import tempfile
> > +import subprocess
> > +
> > +from qemu_test import LinuxKernelTest, Asset> +from aspeed import
> > +AspeedTest from qemu_test import exec_command_and_wait_for_pattern,
> > +skipIfMissingCommands
> > +
>
> Please add an extra blank line
>
> > +class AspeedOtpMemoryTest(AspeedTest):
> > + # AST2600 SDK image
> > + ASSET_SDK_V907_AST2600 = Asset(
> > +
> 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.07/a
> st2600-default-obmc.tar.gz',
> > +
> >
> +'cb6c08595bcbba1672ce716b068ba4e48eda1ed9abe78a07b30392ba2278fe
> ba')
>
> Please update first all functional tests with the new SDK v9.07 images.
>
> > +
> > + # AST1030 Zephyr image
> > + ASSET_ZEPHYR_3_02 = Asset(
> > +
> 'https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.03.02/
> ast1030-evb-demo.zip',
> > +
> > +
> '1ec83caab3ddd5d09481772801be7210e222cb015ce22ec6fffb8a76956dcd4f'
> )
>
> Same for Zephyr images
>
> > +
> > + def generate_otpmem_image(self):
> > + path = self.scratch_file("otpmem.img")
> > + pattern = b'\x00\x00\x00\x00\xff\xff\xff\xff' * (16 * 1024 // 8)
> > + with open(path, "wb") as f:
> > + f.write(pattern)
> > + return path
> > +
> > + def test_ast2600_otp_blockdev_device(self):
> > + image_path =
> self.archive_extract(self.ASSET_SDK_V907_AST2600)
> > + otp_img = self.generate_otpmem_image()
> > + self.vm.set_machine("ast2600-evb")
>
> Please move self.vm.set_machine() at the top of the routine.
>
>
> Thanks,
>
> C.
>
>
>
> > + self.vm.set_console()
> > + self.vm.add_args(
> > + "-blockdev",
> f"driver=file,filename={otp_img},node-name=otp",
> > + "-global", "aspeed-otp.drive=otp",
> > + )
> > +
> self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-default",
> "image-bmc"))
> > + self.wait_for_console_pattern("ast2600-default login:")
> > +
> > + def test_ast1030_otp_blockdev_device(self):
> > + kernel_name = "ast1030-evb-demo-3/zephyr.elf"
> > + kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_02,
> member=kernel_name)
> > + otp_img = self.generate_otpmem_image()
> > + self.vm.set_machine("ast1030-evb")
> > + self.vm.set_console()
> > + self.vm.add_args(
> > + "-kernel", kernel_file,
> > + "-blockdev",
> f"driver=file,filename={otp_img},node-name=otp",
> > + "-global", "aspeed-otp.drive=otp",
> > + )
> > + self.vm.launch()
> > + self.wait_for_console_pattern("Booting Zephyr OS")
> > +
> > +if __name__ == '__main__':
> > + AspeedTest.main()
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (8 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Kane Chen via
@ 2025-08-12 9:40 ` Kane Chen via
2025-09-02 5:41 ` [SPAM] " Cédric Le Goater
2025-09-02 5:44 ` [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Cédric Le Goater
10 siblings, 1 reply; 20+ messages in thread
From: Kane Chen via @ 2025-08-12 9:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Add documentation for the OTP memory module used by AST2600 and AST1030
SoCs, and describe options for using a pre-generated image or an
internal buffer. Include example commands for configuration and image
generation.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index bf18c56347..6317c0e910 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -243,6 +243,37 @@ under Linux), use :
-M ast2500-evb,bmc-console=uart3
+OTP Option
+^^^^^^^^^^
+
+Both the AST2600 and AST1030 chips use the same One Time Programmable
+(OTP) memory module, which is utilized for configuration, key storage,
+and storing user-programmable data. This OTP memory module is managed
+by the Secure Boot Controller (SBC). The following options can be
+specified or omitted based on your needs.
+
+ * When the options are specified, the pre-generated configuration
+ file will be used as the OTP memory storage.
+
+ * When the options are omitted, an internal memory buffer will be
+ used to store the OTP memory data.
+
+.. code-block:: bash
+
+ -blockdev driver=file,filename=otpmem.img,node-name=otp \
+ -global aspeed-otp.drive=otp \
+
+The following bash command can be used to generate a default
+configuration file for OTP memory:
+
+.. code-block:: bash
+
+ if [ ! -f otpmem.img ]; then
+ for i in $(seq 1 2048); do
+ printf '\x00\x00\x00\x00\xff\xff\xff\xff'
+ done > otpmem.img
+ fi
+
Aspeed 2700 family boards (``ast2700-evb``)
==================================================================
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [SPAM] [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options
2025-08-12 9:40 ` [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Kane Chen via
@ 2025-09-02 5:41 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:41 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Add documentation for the OTP memory module used by AST2600 and AST1030
> SoCs, and describe options for using a pre-generated image or an
> internal buffer. Include example commands for configuration and image
> generation.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> docs/system/arm/aspeed.rst | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
> index bf18c56347..6317c0e910 100644
> --- a/docs/system/arm/aspeed.rst
> +++ b/docs/system/arm/aspeed.rst
> @@ -243,6 +243,37 @@ under Linux), use :
>
> -M ast2500-evb,bmc-console=uart3
>
> +OTP Option
> +^^^^^^^^^^
> +
> +Both the AST2600 and AST1030 chips use the same One Time Programmable
> +(OTP) memory module, which is utilized for configuration, key storage,
> +and storing user-programmable data. This OTP memory module is managed
> +by the Secure Boot Controller (SBC). The following options can be
> +specified or omitted based on your needs.
> +
> + * When the options are specified, the pre-generated configuration
> + file will be used as the OTP memory storage.
> +
> + * When the options are omitted, an internal memory buffer will be
> + used to store the OTP memory data.
> +
> +.. code-block:: bash
> +
> + -blockdev driver=file,filename=otpmem.img,node-name=otp \
> + -global aspeed-otp.drive=otp \
> +
> +The following bash command can be used to generate a default
> +configuration file for OTP memory:
> +
> +.. code-block:: bash
> +
> + if [ ! -f otpmem.img ]; then
> + for i in $(seq 1 2048); do
> + printf '\x00\x00\x00\x00\xff\xff\xff\xff'
> + done > otpmem.img
> + fi
> +
> Aspeed 2700 family boards (``ast2700-evb``)
> ==================================================================
>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs
2025-08-12 9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
` (9 preceding siblings ...)
2025-08-12 9:40 ` [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Kane Chen via
@ 2025-09-02 5:44 ` Cédric Le Goater
2025-09-02 6:05 ` Kane Chen
10 siblings, 1 reply; 20+ messages in thread
From: Cédric Le Goater @ 2025-09-02 5:44 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
Hello Kane,
On 8/12/25 11:39, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> This patch series extends the QEMU model for the ASPEED OTP (One-Time
> Programmable) memory device with block backend support and tighter
> integration with the SoC and machine configuration.
>
> The OTP model simulates a simple fuse array used in ASPEED SoCs for
> secure boot, configuration, key storage, and user-programmable data.
> The updated model adds support for loading initial OTP content from a
> file via the QEMU CLI.
>
> Example usage:
> ./qemu-system-arm \
> -machine ast2600-evb \
> -blockdev driver=file,filename=otpmem.img,node-name=otp \
> -global aspeed-otp.drive=otp \
> ...
>
> Any feedback or suggestions are appreciated!
>
> Kane
> ---
>
> ChangeLog
> ---------
> v5:
> - Add OTP programming semantics and tracing
> - Integrate OTP into AST1030 SoC
> - Add CAMP2 register support for reading both DWORDs of OTP data
> entries
> - Handle voltage mode write commands to avoid misreporting valid
> requests as "Unknown command"
> - Add functional test to verify firmware boot with a pre-configured
> OTP image
> - Add documentation for OTP memory options in QEMU
>
> v4:
> - Add a 'drive' property to allow backing OTP data with a block device
> - Expose a machine parameter (`-machine otpmem=XXX`) for convenient
> aliasing of the OTP drive via QOM path
>
> v3:
> - Switched to object_property_set_int() for setting "size"
> - Simplified qdev_realize() error handling by passing errp directly
> - Added "drive" property to OTP model for future extensibility
>
> v2:
> - Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to hw/nvram/
> - Move OTP device realization from instance_init to the realize function
> - Improve error logging with qemu_log_mask() and remove unused error propagation
>
> v1:
> - Initial version
>
> ---
>
> Kane-Chen-AS (10):
> hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
> hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
> hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
> hw/nvram/aspeed_otp: Add 'drive' property to support block backend
> hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
> hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
> hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
> hw/misc/aspeed_sbc: Handle OTP write command for voltage mode
> registers
> tests/function/aspeed: Add OTP functional test
> docs/system/arm/aspeed: Document OTP memory options
>
> docs/system/arm/aspeed.rst | 31 ++++
> include/hw/misc/aspeed_sbc.h | 6 +
> include/hw/nvram/aspeed_otp.h | 33 ++++
> hw/arm/aspeed_ast10x0.c | 2 +-
> hw/arm/aspeed_ast2600.c | 2 +-
> hw/misc/aspeed_sbc.c | 196 ++++++++++++++++++++++++
> hw/nvram/aspeed_otp.c | 190 +++++++++++++++++++++++
> hw/misc/trace-events | 6 +
> hw/nvram/meson.build | 4 +
> hw/nvram/trace-events | 5 +
> tests/functional/meson.build | 2 +
> tests/functional/test_arm_aspeed_otp.py | 55 +++++++
> 12 files changed, 530 insertions(+), 2 deletions(-)
> create mode 100644 include/hw/nvram/aspeed_otp.h
> create mode 100644 hw/nvram/aspeed_otp.c
> create mode 100644 tests/functional/test_arm_aspeed_otp.py
>
I will queue patches 1-8,10 in aspeed-next. No need to resend.
Please address the comments on patch 9 in a new series, Cc: Thomas.
Thanks,
C.
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs
2025-09-02 5:44 ` [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Cédric Le Goater
@ 2025-09-02 6:05 ` Kane Chen
0 siblings, 0 replies; 20+ messages in thread
From: Kane Chen @ 2025-09-02 6:05 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
Thank you for your help and the review. I’ll start a new thread to discuss the test script.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, September 2, 2025 1:44 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration,
> tests, and docs
>
> Hello Kane,
>
> On 8/12/25 11:39, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > This patch series extends the QEMU model for the ASPEED OTP (One-Time
> > Programmable) memory device with block backend support and tighter
> > integration with the SoC and machine configuration.
> >
> > The OTP model simulates a simple fuse array used in ASPEED SoCs for
> > secure boot, configuration, key storage, and user-programmable data.
> > The updated model adds support for loading initial OTP content from a
> > file via the QEMU CLI.
> >
> > Example usage:
> > ./qemu-system-arm \
> > -machine ast2600-evb \
> > -blockdev driver=file,filename=otpmem.img,node-name=otp \
> > -global aspeed-otp.drive=otp \
> > ...
> >
> > Any feedback or suggestions are appreciated!
> >
> > Kane
> > ---
> >
> > ChangeLog
> > ---------
> > v5:
> > - Add OTP programming semantics and tracing
> > - Integrate OTP into AST1030 SoC
> > - Add CAMP2 register support for reading both DWORDs of OTP data
> > entries
> > - Handle voltage mode write commands to avoid misreporting valid
> > requests as "Unknown command"
> > - Add functional test to verify firmware boot with a pre-configured
> > OTP image
> > - Add documentation for OTP memory options in QEMU
> >
> > v4:
> > - Add a 'drive' property to allow backing OTP data with a block device
> > - Expose a machine parameter (`-machine otpmem=XXX`) for convenient
> > aliasing of the OTP drive via QOM path
> >
> > v3:
> > - Switched to object_property_set_int() for setting "size"
> > - Simplified qdev_realize() error handling by passing errp directly
> > - Added "drive" property to OTP model for future extensibility
> >
> > v2:
> > - Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to
> > hw/nvram/
> > - Move OTP device realization from instance_init to the realize
> > function
> > - Improve error logging with qemu_log_mask() and remove unused error
> > propagation
> >
> > v1:
> > - Initial version
> >
> > ---
> >
> > Kane-Chen-AS (10):
> > hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
> > hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
> > hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
> > hw/nvram/aspeed_otp: Add 'drive' property to support block backend
> > hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
> > hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
> > hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
> > hw/misc/aspeed_sbc: Handle OTP write command for voltage mode
> > registers
> > tests/function/aspeed: Add OTP functional test
> > docs/system/arm/aspeed: Document OTP memory options
> >
> > docs/system/arm/aspeed.rst | 31 ++++
> > include/hw/misc/aspeed_sbc.h | 6 +
> > include/hw/nvram/aspeed_otp.h | 33 ++++
> > hw/arm/aspeed_ast10x0.c | 2 +-
> > hw/arm/aspeed_ast2600.c | 2 +-
> > hw/misc/aspeed_sbc.c | 196
> ++++++++++++++++++++++++
> > hw/nvram/aspeed_otp.c | 190
> +++++++++++++++++++++++
> > hw/misc/trace-events | 6 +
> > hw/nvram/meson.build | 4 +
> > hw/nvram/trace-events | 5 +
> > tests/functional/meson.build | 2 +
> > tests/functional/test_arm_aspeed_otp.py | 55 +++++++
> > 12 files changed, 530 insertions(+), 2 deletions(-)
> > create mode 100644 include/hw/nvram/aspeed_otp.h
> > create mode 100644 hw/nvram/aspeed_otp.c
> > create mode 100644 tests/functional/test_arm_aspeed_otp.py
> >
>
> I will queue patches 1-8,10 in aspeed-next. No need to resend.
>
> Please address the comments on patch 9 in a new series, Cc: Thomas.
>
> Thanks,
>
> C.
>
>
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread