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Tsirkin" , mtosatti@redhat.com Subject: [PATCH v4 8/8] tcg: move interrupt caching and single step masking closer to user Date: Thu, 14 Aug 2025 18:06:00 +0200 Message-ID: <20250814160600.2327672-9-imammedo@redhat.com> In-Reply-To: <20250814160600.2327672-1-imammedo@redhat.com> References: <20250814160600.2327672-1-imammedo@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org in cpu_handle_interrupt() the only place where cached interrupt_request might have effect is when CPU_INTERRUPT_SSTEP_MASK applied and cached interrupt_request handed over to cpu_exec_interrupt() and need_replay_interrupt(). Simplify code by moving interrupt_request caching and CPU_INTERRUPT_SSTEP_MASK masking into the block where it actually matters and drop reloading cached value from CPUState:interrupt_request as the rest of the code directly uses CPUState:interrupt_request. Signed-off-by: Igor Mammedov --- accel/tcg/cpu-exec.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 1269c2c6ba..82867f456c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -779,13 +779,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); if (unlikely(cpu_test_interrupt(cpu, ~0))) { - int interrupt_request; bql_lock(); - interrupt_request = cpu->interrupt_request; - if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { - /* Mask out external interrupts for this step. */ - interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; - } if (cpu_test_interrupt(cpu, CPU_INTERRUPT_DEBUG)) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; cpu->exception_index = EXCP_DEBUG; @@ -804,6 +798,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, return true; } else { const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + int interrupt_request = cpu->interrupt_request; if (cpu_test_interrupt(cpu, CPU_INTERRUPT_RESET)) { replay_interrupt(); @@ -812,6 +807,11 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, return true; } + if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { + /* Mask out external interrupts for this step. */ + interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; + } + /* * The target hook has 3 exit conditions: * False when the interrupt isn't processed, @@ -836,9 +836,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index = -1; *last_tb = NULL; } - /* The target hook may have updated the 'cpu->interrupt_request'; - * reload the 'interrupt_request' value */ - interrupt_request = cpu->interrupt_request; } #endif /* !CONFIG_USER_ONLY */ if (cpu_test_interrupt(cpu, CPU_INTERRUPT_EXITTB)) { -- 2.47.1