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From: "Corvin Köhne" <corvin.koehne@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Corvin Köhne" <c.koehne@beckhoff.com>,
	qemu-arm@nongnu.org, "Kevin Wolf" <kwolf@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Yannick Voßen" <y.vossen@beckhoff.com>,
	"Hanna Reitz" <hreitz@redhat.com>,
	qemu-block@nongnu.org, YannickV <Y.Vossen@beckhoff.com>
Subject: [PATCH v2 12/14] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
Date: Fri, 15 Aug 2025 11:01:10 +0200	[thread overview]
Message-ID: <20250815090113.141641-13-corvin.koehne@gmail.com> (raw)
In-Reply-To: <20250815090113.141641-1-corvin.koehne@gmail.com>

From: YannickV <Y.Vossen@beckhoff.com>

The is25lp016d has 4 Block Write Protect Bits. BP3 specifies
whether the upper or lower range should be protected. Therefore,
we add the HAS_SR_TB flag to the is25lp016d flags.

Signed-off-by: Yannick Voßen <y.vossen@beckhoff.com>
---
 hw/block/m25p80.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b84c6afb32..4c9d79ec44 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -217,7 +217,8 @@ static const FlashPartInfo known_devices[] = {
     /* ISSI */
     { INFO("is25lq040b",  0x9d4013,      0,  64 << 10,   8, ER_4K) },
     { INFO("is25lp080d",  0x9d6014,      0,  64 << 10,  16, ER_4K) },
-    { INFO("is25lp016d",  0x9d6015,      0,  64 << 10,  32, ER_4K) },
+    { INFO("is25lp016d",  0x9d6015,      0,  64 << 10,  32,
+           ER_4K | HAS_SR_TB) },
     { INFO("is25lp032",   0x9d6016,      0,  64 << 10,  64, ER_4K) },
     { INFO("is25lp064",   0x9d6017,      0,  64 << 10, 128, ER_4K) },
     { INFO("is25lp128",   0x9d6018,      0,  64 << 10, 256, ER_4K) },
-- 
2.50.1



  parent reply	other threads:[~2025-08-15  9:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-15  9:00 [PATCH v2 00/14] hw/arm: add Beckhoff CX7200 board Corvin Köhne
2025-08-15  9:00 ` [PATCH v2 01/14] hw/timer: Make frequency configurable Corvin Köhne
2025-08-19 16:37   ` Peter Maydell
2025-08-19 16:41   ` Peter Maydell
2025-08-15  9:01 ` [PATCH v2 02/14] hw/timer: Make PERIPHCLK period configurable Corvin Köhne
2025-08-19 16:38   ` Peter Maydell
2025-08-15  9:01 ` [PATCH v2 03/14] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Corvin Köhne
2025-08-15  9:01 ` [PATCH v2 04/14] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Corvin Köhne
2025-08-24 15:47   ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 05/14] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Corvin Köhne
2025-08-24 16:09   ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 06/14] hw/dma/zynq-devcfg: Simulate dummy PL reset Corvin Köhne
2025-08-24 15:53   ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 07/14] hw/dma/zynq-devcfg: Indicate power-up status of PL Corvin Köhne
2025-08-24 16:11   ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 08/14] hw/dma/zynq-devcfg: Fix register memory Corvin Köhne
2025-08-15  9:01 ` [PATCH v2 09/14] hw/misc: Add dummy ZYNQ DDR controller Corvin Köhne
2025-08-19 15:43   ` Peter Maydell
2025-08-24 16:24     ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 10/14] hw/misc/zynq_slcr: Add logic for DCI configuration Corvin Köhne
2025-08-24 16:41   ` Edgar E. Iglesias
2025-08-15  9:01 ` [PATCH v2 11/14] hw/misc: Add Beckhoff CCAT device Corvin Köhne
2025-08-19 16:03   ` Peter Maydell
2025-08-15  9:01 ` Corvin Köhne [this message]
2025-08-15  9:01 ` [PATCH v2 13/14] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Corvin Köhne
2025-08-15  9:01 ` [PATCH v2 14/14] docs/system/arm: Add support " Corvin Köhne
2025-08-15 18:06 ` [PATCH v2 00/14] hw/arm: add Beckhoff CX7200 board Peter Maydell
2025-08-19 16:40   ` Peter Maydell
2025-08-24 16:51     ` Edgar E. Iglesias

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