* [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts
@ 2025-08-20 14:21 Philippe Mathieu-Daudé
2025-08-20 14:21 ` [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini,
Thomas Huth, Huacai Chen, Jiaxun Yang
32-bit hosts are deprecated since v10.0. 2 releases later (as
of v10.2) we can remove such code. Start with MIPS TCG backend.
Remove related buildsys and testing.
Based-on: <20250820134937.45077-1-philmd@linaro.org>
Philippe Mathieu-Daudé (5):
docker: Remove 32-bit MIPS toolchain from debian-all-test image
gitlab: Stop cross-testing for 32-bit MIPS hosts
docker: Stop building 32-bit MIPS images
tcg/mips: Check O32/N32/64 ABI definitions actually exist
tcg/mips: Remove support for 32-bit hosts
configure | 2 -
tcg/mips/tcg-target-has.h | 2 -
tcg/mips/tcg-target-reg-bits.h | 5 +-
tcg/mips/tcg-target.c.inc | 282 +++---------------
.gitlab-ci.d/container-cross.yml | 6 -
.gitlab-ci.d/crossbuilds.yml | 14 -
common-user/host/mips/safe-syscall.inc.S | 4 +-
tests/docker/Makefile.include | 2 +-
.../dockerfiles/debian-all-test-cross.docker | 4 -
.../dockerfiles/debian-mipsel-cross.docker | 180 -----------
tests/lcitool/refresh | 5 -
11 files changed, 42 insertions(+), 464 deletions(-)
delete mode 100644 tests/docker/dockerfiles/debian-mipsel-cross.docker
--
2.51.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé @ 2025-08-20 14:21 ` Philippe Mathieu-Daudé 2025-08-22 11:23 ` Alex Bennée 2025-08-20 14:21 ` [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw) To: qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang In commit d3322023bfe ("configure: unify again the case arms in probe_target_compiler") we lost coverage of 32-bit MIPS with the debian-all-test image. No need to keep installing the toolchain. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- tests/docker/dockerfiles/debian-all-test-cross.docker | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker b/tests/docker/dockerfiles/debian-all-test-cross.docker index 420a4e33e60..bc74d65a634 100644 --- a/tests/docker/dockerfiles/debian-all-test-cross.docker +++ b/tests/docker/dockerfiles/debian-all-test-cross.docker @@ -40,14 +40,10 @@ ENV AVAILABLE_COMPILERS gcc-aarch64-linux-gnu \ libc6-dev-arm64-cross \ gcc-arm-linux-gnueabihf \ libc6-dev-armhf-cross \ - gcc-mips-linux-gnu \ - libc6-dev-mips-cross \ gcc-mips64-linux-gnuabi64 \ libc6-dev-mips64-cross \ gcc-mips64el-linux-gnuabi64 \ libc6-dev-mips64el-cross \ - gcc-mipsel-linux-gnu \ - libc6-dev-mipsel-cross \ gcc-powerpc64le-linux-gnu \ libc6-dev-ppc64el-cross \ gcc-riscv64-linux-gnu \ -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image 2025-08-20 14:21 ` [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé @ 2025-08-22 11:23 ` Alex Bennée 2025-08-22 14:49 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 12+ messages in thread From: Alex Bennée @ 2025-08-22 11:23 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Richard Henderson, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang Philippe Mathieu-Daudé <philmd@linaro.org> writes: > In commit d3322023bfe ("configure: unify again the case arms in > probe_target_compiler") we lost coverage of 32-bit MIPS with the > debian-all-test image. No need to keep installing the toolchain. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > tests/docker/dockerfiles/debian-all-test-cross.docker | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker b/tests/docker/dockerfiles/debian-all-test-cross.docker > index 420a4e33e60..bc74d65a634 100644 > --- a/tests/docker/dockerfiles/debian-all-test-cross.docker > +++ b/tests/docker/dockerfiles/debian-all-test-cross.docker > @@ -40,14 +40,10 @@ ENV AVAILABLE_COMPILERS gcc-aarch64-linux-gnu \ > libc6-dev-arm64-cross \ > gcc-arm-linux-gnueabihf \ > libc6-dev-armhf-cross \ > - gcc-mips-linux-gnu \ > - libc6-dev-mips-cross \ > gcc-mips64-linux-gnuabi64 \ > libc6-dev-mips64-cross \ > gcc-mips64el-linux-gnuabi64 \ > libc6-dev-mips64el-cross \ > - gcc-mipsel-linux-gnu \ > - libc6-dev-mipsel-cross \ > gcc-powerpc64le-linux-gnu \ > libc6-dev-ppc64el-cross \ > gcc-riscv64-linux-gnu \ You also need to remove the references in configure: hppa|m68k|mips|riscv64|sparc64) container_image=debian-all-test-cross ;; mips64) container_image=debian-all-test-cross container_cross_prefix=mips64-linux-gnuabi64- ;; -- Alex Bennée Virtualisation Tech Lead @ Linaro ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image 2025-08-22 11:23 ` Alex Bennée @ 2025-08-22 14:49 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-22 14:49 UTC (permalink / raw) To: Alex Bennée Cc: qemu-devel, Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Richard Henderson, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang On 22/8/25 13:23, Alex Bennée wrote: > Philippe Mathieu-Daudé <philmd@linaro.org> writes: > >> In commit d3322023bfe ("configure: unify again the case arms in >> probe_target_compiler") we lost coverage of 32-bit MIPS with the >> debian-all-test image. No need to keep installing the toolchain. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> tests/docker/dockerfiles/debian-all-test-cross.docker | 4 ---- >> 1 file changed, 4 deletions(-) >> >> diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker b/tests/docker/dockerfiles/debian-all-test-cross.docker >> index 420a4e33e60..bc74d65a634 100644 >> --- a/tests/docker/dockerfiles/debian-all-test-cross.docker >> +++ b/tests/docker/dockerfiles/debian-all-test-cross.docker >> @@ -40,14 +40,10 @@ ENV AVAILABLE_COMPILERS gcc-aarch64-linux-gnu \ >> libc6-dev-arm64-cross \ >> gcc-arm-linux-gnueabihf \ >> libc6-dev-armhf-cross \ >> - gcc-mips-linux-gnu \ >> - libc6-dev-mips-cross \ >> gcc-mips64-linux-gnuabi64 \ >> libc6-dev-mips64-cross \ >> gcc-mips64el-linux-gnuabi64 \ >> libc6-dev-mips64el-cross \ >> - gcc-mipsel-linux-gnu \ >> - libc6-dev-mipsel-cross \ >> gcc-powerpc64le-linux-gnu \ >> libc6-dev-ppc64el-cross \ >> gcc-riscv64-linux-gnu \ > > You also need to remove the references in configure: > > hppa|m68k|mips|riscv64|sparc64) > container_image=debian-all-test-cross > ;; OK. > mips64) > container_image=debian-all-test-cross > container_cross_prefix=mips64-linux-gnuabi64- > ;; We aren't removing mips64 yet. We will but since the reason is different, it will be in another series. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-08-20 14:21 ` [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé @ 2025-08-20 14:21 ` Philippe Mathieu-Daudé 2025-08-25 12:31 ` Thomas Huth 2025-08-20 14:21 ` [PATCH 3/5] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw) To: qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Next commits will remove support for 32-bit MIPS hosts. Stop cross-building QEMU on our CI. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- .gitlab-ci.d/container-cross.yml | 6 ------ .gitlab-ci.d/crossbuilds.yml | 14 -------------- 2 files changed, 20 deletions(-) diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml index 8d3be53b75b..0fd7341afac 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -52,12 +52,6 @@ mips64el-debian-cross-container: variables: NAME: debian-mips64el-cross -mipsel-debian-cross-container: - extends: .container_job_template - stage: containers - variables: - NAME: debian-mipsel-cross - ppc64el-debian-cross-container: extends: .container_job_template stage: containers diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 3f76c901ba8..721aea77a27 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -68,20 +68,6 @@ cross-i686-tci: # would otherwise be using a parallelism of 9. MAKE_CHECK_ARGS: check check-tcg -j2 -cross-mipsel-system: - extends: .cross_system_build_job - needs: - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - -cross-mipsel-user: - extends: .cross_user_build_job - needs: - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - cross-mips64el-system: extends: .cross_system_build_job needs: -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts 2025-08-20 14:21 ` [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé @ 2025-08-25 12:31 ` Thomas Huth 0 siblings, 0 replies; 12+ messages in thread From: Thomas Huth @ 2025-08-25 12:31 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Paolo Bonzini, Huacai Chen, Jiaxun Yang On 20/08/2025 16.21, Philippe Mathieu-Daudé wrote: > 32-bit host support is deprecated since commit 6d701c9bac1 > ("meson: Deprecate 32-bit host support"). Next commits will > remove support for 32-bit MIPS hosts. Stop cross-building > QEMU on our CI. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > .gitlab-ci.d/container-cross.yml | 6 ------ > .gitlab-ci.d/crossbuilds.yml | 14 -------------- > 2 files changed, 20 deletions(-) Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/5] docker: Stop building 32-bit MIPS images 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-08-20 14:21 ` [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé 2025-08-20 14:21 ` [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé @ 2025-08-20 14:21 ` Philippe Mathieu-Daudé 2025-08-25 12:33 ` Thomas Huth 2025-08-20 14:21 ` [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist Philippe Mathieu-Daudé ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw) To: qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Besides, the Debian distribution we are using to cross-build dropped support for MIPS as of Debian 13 [*]: From trixie, the architectures mipsel and mips64el are no longer supported by Debian. Users of these architectures are advised to switch to different hardware. Next commits will remove support for 32-bit MIPS hosts. Stop building the mipsel Docker image. [*] https://www.debian.org/releases/trixie/release-notes/issues.en.html#mips-architectures-removed Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- configure | 2 - tests/docker/Makefile.include | 2 +- .../dockerfiles/debian-mipsel-cross.docker | 180 ------------------ tests/lcitool/refresh | 5 - 4 files changed, 1 insertion(+), 188 deletions(-) delete mode 100644 tests/docker/dockerfiles/debian-mipsel-cross.docker diff --git a/configure b/configure index 274a7787642..2d85a6a156c 100755 --- a/configure +++ b/configure @@ -1347,8 +1347,6 @@ fi : ${cross_prefix_microblaze="microblaze-linux-musl-"} : ${cross_prefix_mips64el="mips64el-linux-gnuabi64-"} : ${cross_prefix_mips64="mips64-linux-gnuabi64-"} -: ${cross_prefix_mipsel="mipsel-linux-gnu-"} -: ${cross_prefix_mips="mips-linux-gnu-"} : ${cross_prefix_ppc="powerpc-linux-gnu-"} : ${cross_prefix_ppc64="powerpc64-linux-gnu-"} : ${cross_prefix_ppc64le="$cross_prefix_ppc64"} diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 3959d8a028a..ac8ca1fe3a0 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -82,7 +82,7 @@ endif # For non-x86 hosts not all cross-compilers have been packaged ifneq ($(HOST_ARCH),x86_64) -DOCKER_PARTIAL_IMAGES += debian-mipsel-cross debian-mips64el-cross +DOCKER_PARTIAL_IMAGES += debian-mips64el-cross DOCKER_PARTIAL_IMAGES += debian-ppc64el-cross DOCKER_PARTIAL_IMAGES += debian-s390x-cross DOCKER_PARTIAL_IMAGES += fedora diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker b/tests/docker/dockerfiles/debian-mipsel-cross.docker deleted file mode 100644 index 4d3e5d711bd..00000000000 --- a/tests/docker/dockerfiles/debian-mipsel-cross.docker +++ /dev/null @@ -1,180 +0,0 @@ -# THIS FILE WAS AUTO-GENERATED -# -# $ lcitool dockerfile --layers all --cross-arch mipsel debian-12 qemu -# -# https://gitlab.com/libvirt/libvirt-ci - -FROM docker.io/library/debian:12-slim - -RUN export DEBIAN_FRONTEND=noninteractive && \ - apt-get update && \ - apt-get install -y eatmydata && \ - eatmydata apt-get dist-upgrade -y && \ - eatmydata apt-get install --no-install-recommends -y \ - bash \ - bc \ - bindgen \ - bison \ - bsdextrautils \ - bzip2 \ - ca-certificates \ - ccache \ - dbus \ - debianutils \ - diffutils \ - exuberant-ctags \ - findutils \ - flex \ - gcc \ - gcovr \ - gettext \ - git \ - hostname \ - libglib2.0-dev \ - llvm \ - locales \ - make \ - meson \ - mtools \ - ncat \ - ninja-build \ - openssh-client \ - pkgconf \ - python3 \ - python3-numpy \ - python3-opencv \ - python3-pillow \ - python3-pip \ - python3-sphinx \ - python3-sphinx-rtd-theme \ - python3-venv \ - python3-yaml \ - rpm2cpio \ - rustc-web \ - sed \ - socat \ - sparse \ - swtpm \ - tar \ - tesseract-ocr \ - tesseract-ocr-eng \ - vulkan-tools \ - xorriso \ - zstd && \ - eatmydata apt-get autoremove -y && \ - eatmydata apt-get autoclean -y && \ - sed -Ei 's,^# (en_US\.UTF-8 .*)$,\1,' /etc/locale.gen && \ - dpkg-reconfigure locales && \ - rm -f /usr/lib*/python3*/EXTERNALLY-MANAGED - -ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers" -ENV LANG "en_US.UTF-8" -ENV MAKE "/usr/bin/make" -ENV NINJA "/usr/bin/ninja" -ENV PYTHON "/usr/bin/python3" - -RUN export DEBIAN_FRONTEND=noninteractive && \ - dpkg --add-architecture mipsel && \ - eatmydata apt-get update && \ - eatmydata apt-get dist-upgrade -y && \ - eatmydata apt-get install --no-install-recommends -y dpkg-dev && \ - eatmydata apt-get install --no-install-recommends -y \ - gcc-mipsel-linux-gnu \ - libaio-dev:mipsel \ - libasound2-dev:mipsel \ - libattr1-dev:mipsel \ - libbpf-dev:mipsel \ - libbrlapi-dev:mipsel \ - libbz2-dev:mipsel \ - libc6-dev:mipsel \ - libcacard-dev:mipsel \ - libcap-ng-dev:mipsel \ - libcapstone-dev:mipsel \ - libcbor-dev:mipsel \ - libcmocka-dev:mipsel \ - libcurl4-gnutls-dev:mipsel \ - libdaxctl-dev:mipsel \ - libdrm-dev:mipsel \ - libepoxy-dev:mipsel \ - libfdt-dev:mipsel \ - libffi-dev:mipsel \ - libfuse3-dev:mipsel \ - libgbm-dev:mipsel \ - libgcrypt20-dev:mipsel \ - libglib2.0-dev:mipsel \ - libglusterfs-dev:mipsel \ - libgnutls28-dev:mipsel \ - libgtk-3-dev:mipsel \ - libgtk-vnc-2.0-dev:mipsel \ - libibverbs-dev:mipsel \ - libiscsi-dev:mipsel \ - libjemalloc-dev:mipsel \ - libjpeg62-turbo-dev:mipsel \ - libjson-c-dev:mipsel \ - liblttng-ust-dev:mipsel \ - liblzo2-dev:mipsel \ - libncursesw5-dev:mipsel \ - libnfs-dev:mipsel \ - libnuma-dev:mipsel \ - libpam0g-dev:mipsel \ - libpcre2-dev:mipsel \ - libpipewire-0.3-dev:mipsel \ - libpixman-1-dev:mipsel \ - libpng-dev:mipsel \ - libpulse-dev:mipsel \ - librbd-dev:mipsel \ - librdmacm-dev:mipsel \ - libsasl2-dev:mipsel \ - libsdl2-dev:mipsel \ - libsdl2-image-dev:mipsel \ - libseccomp-dev:mipsel \ - libselinux1-dev:mipsel \ - libslirp-dev:mipsel \ - libsnappy-dev:mipsel \ - libsndio-dev:mipsel \ - libspice-protocol-dev:mipsel \ - libspice-server-dev:mipsel \ - libssh-dev:mipsel \ - libsystemd-dev:mipsel \ - libtasn1-6-dev:mipsel \ - libudev-dev:mipsel \ - liburing-dev:mipsel \ - libusb-1.0-0-dev:mipsel \ - libusbredirhost-dev:mipsel \ - libvdeplug-dev:mipsel \ - libvirglrenderer-dev:mipsel \ - libvte-2.91-dev:mipsel \ - libxdp-dev:mipsel \ - libzstd-dev:mipsel \ - nettle-dev:mipsel \ - systemtap-sdt-dev:mipsel \ - zlib1g-dev:mipsel && \ - eatmydata apt-get autoremove -y && \ - eatmydata apt-get autoclean -y && \ - mkdir -p /usr/local/share/meson/cross && \ - printf "[binaries]\n\ -c = '/usr/bin/mipsel-linux-gnu-gcc'\n\ -ar = '/usr/bin/mipsel-linux-gnu-gcc-ar'\n\ -strip = '/usr/bin/mipsel-linux-gnu-strip'\n\ -pkgconfig = '/usr/bin/mipsel-linux-gnu-pkg-config'\n\ -\n\ -[host_machine]\n\ -system = 'linux'\n\ -cpu_family = 'mips'\n\ -cpu = 'mipsel'\n\ -endian = 'little'\n" > /usr/local/share/meson/cross/mipsel-linux-gnu && \ - dpkg-query --showformat '${Package}_${Version}_${Architecture}\n' --show > /packages.txt && \ - mkdir -p /usr/libexec/ccache-wrappers && \ - ln -s /usr/bin/ccache /usr/libexec/ccache-wrappers/mipsel-linux-gnu-cc && \ - ln -s /usr/bin/ccache /usr/libexec/ccache-wrappers/mipsel-linux-gnu-gcc - -ENV ABI "mipsel-linux-gnu" -ENV MESON_OPTS "--cross-file=mipsel-linux-gnu" -ENV RUST_TARGET "mipsel-unknown-linux-gnu" -ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsel-linux-gnu- -ENV DEF_TARGET_LIST mipsel-softmmu,mipsel-linux-user -# As a final step configure the user (if env is defined) -ARG USER -ARG UID -RUN if [ "${USER}" ]; then \ - id ${USER} 2>/dev/null || useradd -u ${UID} -U ${USER}; fi diff --git a/tests/lcitool/refresh b/tests/lcitool/refresh index d3488b2679e..6a70e1dc497 100755 --- a/tests/lcitool/refresh +++ b/tests/lcitool/refresh @@ -214,11 +214,6 @@ try: trailer=cross_build("mips64el-linux-gnuabi64-", "mips64el-softmmu,mips64el-linux-user")) - generate_dockerfile("debian-mipsel-cross", "debian-12", - cross="mipsel", - trailer=cross_build("mipsel-linux-gnu-", - "mipsel-softmmu,mipsel-linux-user")) - generate_dockerfile("debian-ppc64el-cross", "debian-12", cross="ppc64le", trailer=cross_build("powerpc64le-linux-gnu-", -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] docker: Stop building 32-bit MIPS images 2025-08-20 14:21 ` [PATCH 3/5] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé @ 2025-08-25 12:33 ` Thomas Huth 0 siblings, 0 replies; 12+ messages in thread From: Thomas Huth @ 2025-08-25 12:33 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Paolo Bonzini, Huacai Chen, Jiaxun Yang On 20/08/2025 16.21, Philippe Mathieu-Daudé wrote: > 32-bit host support is deprecated since commit 6d701c9bac1 > ("meson: Deprecate 32-bit host support"). Besides, the Debian > distribution we are using to cross-build dropped support for > MIPS as of Debian 13 [*]: > > From trixie, the architectures mipsel and mips64el are no > longer supported by Debian. Users of these architectures > are advised to switch to different hardware. > > Next commits will remove support for 32-bit MIPS hosts. Stop > building the mipsel Docker image. > > [*] https://www.debian.org/releases/trixie/release-notes/issues.en.html#mips-architectures-removed > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (2 preceding siblings ...) 2025-08-20 14:21 ` [PATCH 3/5] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé @ 2025-08-20 14:21 ` Philippe Mathieu-Daudé 2025-08-21 21:09 ` Richard Henderson 2025-08-20 14:21 ` [PATCH 5/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-08-21 20:48 ` [PATCH 0/5] " Richard Henderson 5 siblings, 1 reply; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw) To: qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang Similarly noted in libunwind: https://reviews.llvm.org/D38110#895887, when _ABIO32 / _ABIN32 / _ABI64 are not defined (like on OpenBSD) we get: [666/1234] Compiling C object libsystem.a.p/tcg_tcg-common.c.o In file included from ../tcg/tcg-common.c:26: In file included from include/tcg/tcg.h:34: tcg/mips/tcg-target-reg-bits.h:10:18: warning: '_ABIO32' is not defined, evaluates to 0 [-Wundef] #if _MIPS_SIM == _ABIO32 ^ tcg/mips/tcg-target-reg-bits.h:12:20: warning: '_ABIN32' is not defined, evaluates to 0 [-Wundef] #elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 ^ 2 warnings generated. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- tcg/mips/tcg-target-reg-bits.h | 5 +++-- tcg/mips/tcg-target.c.inc | 5 +++-- common-user/host/mips/safe-syscall.inc.S | 4 ++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h index 56fe0a725e9..a957d2312f3 100644 --- a/tcg/mips/tcg-target-reg-bits.h +++ b/tcg/mips/tcg-target-reg-bits.h @@ -7,9 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H -#if _MIPS_SIM == _ABIO32 +#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 # define TCG_TARGET_REG_BITS 32 -#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +#elif (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ + || (defined(_ABI64) && _MIPS_SIM == _ABI64) # define TCG_TARGET_REG_BITS 64 #else # error "Unknown ABI" diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 400eafbab4b..5cdaaaa9286 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -26,7 +26,7 @@ /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 16 -#if _MIPS_SIM == _ABIO32 +#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 # define TCG_TARGET_CALL_STACK_OFFSET 16 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF @@ -135,7 +135,8 @@ static const TCGReg tcg_target_call_iarg_regs[] = { TCG_REG_A1, TCG_REG_A2, TCG_REG_A3, -#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +#if (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ + || (defined(_ABI64) && _MIPS_SIM == _ABI64) TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S index 6a446149704..8857d708dae 100644 --- a/common-user/host/mips/safe-syscall.inc.S +++ b/common-user/host/mips/safe-syscall.inc.S @@ -30,7 +30,7 @@ * arguments being syscall arguments (also 'long'). */ -#if _MIPS_SIM == _ABIO32 +#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 /* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */ #define FRAME 40 #define OFS_S0 32 @@ -47,7 +47,7 @@ NESTED(safe_syscall_base, FRAME, ra) .cfi_adjust_cfa_offset FRAME REG_S s0, OFS_S0(sp) .cfi_rel_offset s0, OFS_S0 -#if _MIPS_SIM == _ABIO32 +#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 /* * The syscall calling convention is nearly the same as C: * we enter with a0 == &signal_pending -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist 2025-08-20 14:21 ` [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist Philippe Mathieu-Daudé @ 2025-08-21 21:09 ` Richard Henderson 0 siblings, 0 replies; 12+ messages in thread From: Richard Henderson @ 2025-08-21 21:09 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang On 8/21/25 00:21, Philippe Mathieu-Daudé wrote: > Similarly noted in libunwind: https://reviews.llvm.org/D38110#895887, > when _ABIO32 / _ABIN32 / _ABI64 are not defined (like on OpenBSD) we > get: > > [666/1234] Compiling C object libsystem.a.p/tcg_tcg-common.c.o > In file included from ../tcg/tcg-common.c:26: > In file included from include/tcg/tcg.h:34: > tcg/mips/tcg-target-reg-bits.h:10:18: warning: '_ABIO32' is not defined, evaluates to 0 [-Wundef] > #if _MIPS_SIM == _ABIO32 > ^ > tcg/mips/tcg-target-reg-bits.h:12:20: warning: '_ABIN32' is not defined, evaluates to 0 [-Wundef] > #elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 > ^ > 2 warnings generated. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > tcg/mips/tcg-target-reg-bits.h | 5 +++-- > tcg/mips/tcg-target.c.inc | 5 +++-- > common-user/host/mips/safe-syscall.inc.S | 4 ++-- > 3 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h > index 56fe0a725e9..a957d2312f3 100644 > --- a/tcg/mips/tcg-target-reg-bits.h > +++ b/tcg/mips/tcg-target-reg-bits.h > @@ -7,9 +7,10 @@ > #ifndef TCG_TARGET_REG_BITS_H > #define TCG_TARGET_REG_BITS_H > > -#if _MIPS_SIM == _ABIO32 > +#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 > # define TCG_TARGET_REG_BITS 32 > -#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 > +#elif (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ > + || (defined(_ABI64) && _MIPS_SIM == _ABI64) > # define TCG_TARGET_REG_BITS 64 > #else > # error "Unknown ABI" Alternately, remove all of this. If we're removing 32-bit hosts, _ABI64 is the only valid answer (N32 has 64-bit registers but 32-bit pointers). r~ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/5] tcg/mips: Remove support for 32-bit hosts 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (3 preceding siblings ...) 2025-08-20 14:21 ` [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist Philippe Mathieu-Daudé @ 2025-08-20 14:21 ` Philippe Mathieu-Daudé 2025-08-21 20:48 ` [PATCH 0/5] " Richard Henderson 5 siblings, 0 replies; 12+ messages in thread From: Philippe Mathieu-Daudé @ 2025-08-20 14:21 UTC (permalink / raw) To: qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"), released as v10.0. The next release being v10.2, we can remove the TCG backend for 32-bit MIPS hosts. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- tcg/mips/tcg-target-has.h | 2 - tcg/mips/tcg-target-reg-bits.h | 4 +- tcg/mips/tcg-target.c.inc | 277 ++++----------------------------- 3 files changed, 35 insertions(+), 248 deletions(-) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index b9eb3385288..88f0145efba 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -39,11 +39,9 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions */ -#if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_ext32s_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#endif /* optional instructions detected at runtime */ #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h index a957d2312f3..e608250c72f 100644 --- a/tcg/mips/tcg-target-reg-bits.h +++ b/tcg/mips/tcg-target-reg-bits.h @@ -7,9 +7,7 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H -#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ +#if (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ || (defined(_ABI64) && _MIPS_SIM == _ABI64) # define TCG_TARGET_REG_BITS 64 #else diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5cdaaaa9286..05b93d69146 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -38,15 +38,6 @@ #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#if TCG_TARGET_REG_BITS == 32 -# define LO_OFF (HOST_BIG_ENDIAN * 4) -# define HI_OFF (4 - LO_OFF) -#else -/* Assert at compile-time that these values are never used for 64-bit. */ -# define LO_OFF ({ qemu_build_not_reached(); 0; }) -# define HI_OFF ({ qemu_build_not_reached(); 0; }) -#endif - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "zero", @@ -90,11 +81,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #define TCG_TMP3 TCG_REG_T7 #define TCG_GUEST_BASE_REG TCG_REG_S7 -#if TCG_TARGET_REG_BITS == 64 #define TCG_REG_TB TCG_REG_S6 -#else -#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) -#endif /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] = { @@ -568,7 +555,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long tmp; int sh, lo; - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { arg = (int32_t)arg; } @@ -576,7 +563,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, if (tcg_out_movi_two(s, ret, arg)) { return; } - assert(TCG_TARGET_REG_BITS == 64); /* Load addresses within 2GB of TB with 1 or 3 insns. */ tmp = tcg_tbrel_diff(s, (void *)arg); @@ -639,7 +625,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; + TCGReg tbreg = TCG_REG_TB; tcg_out_movi_int(s, type, ret, arg, tbreg); } @@ -667,7 +653,6 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); } @@ -710,7 +695,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); } else { @@ -737,7 +721,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_LD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { opc = OPC_LW; } tcg_out_ldst(s, opc, arg, arg1, arg2); @@ -747,7 +731,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_SD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { opc = OPC_SW; } tcg_out_ldst(s, opc, arg, arg1, arg2); @@ -927,72 +911,6 @@ void tcg_out_br(TCGContext *s, TCGLabel *l) tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, l); } -static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - int flags = 0; - - switch (cond) { - case TCG_COND_EQ: - flags |= SETCOND_INV; - /* fall through */ - case TCG_COND_NE: - flags |= SETCOND_NEZ; - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - - default: - tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); - tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), - TCG_TMP1, al, bl); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); - tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - } - return ret | flags; -} - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); - tcg_out_setcond_end(s, ret, tmpflags); -} - -#if TCG_TARGET_REG_BITS != 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 = { - .base.static_constraint = C_O1_I4(r, r, r, rz, rz), - .out = tgen_setcond2, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); - TCGReg tmp = tmpflags & ~SETCOND_FLAGS; - MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; - - tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); - tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); - tcg_out_nop(s); -} - -#if TCG_TARGET_REG_BITS != 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 = { - .base.static_constraint = C_O0_I4(r, r, rz, rz), - .out = tgen_brcond2, -}; - static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) @@ -1198,7 +1116,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); /* Extract the TLB index from the address into TMP3. */ - if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { @@ -1210,7 +1128,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); /* Load the tlb comparator. */ - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HOST_BIG_ENDIAN * 4); } else { @@ -1227,8 +1145,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, */ tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask); if (a_mask < s_mask) { - tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 - || addr_type == TCG_TYPE_I32 + tcg_out_opc_imm(s, (addr_type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU), TCG_TMP2, addr, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); @@ -1237,7 +1154,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP2, addr); addr = TCG_TMP2; } @@ -1270,7 +1187,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } base = addr; - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_A0, base); base = TCG_REG_A0; } @@ -1306,7 +1223,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { + if (type == TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1316,15 +1233,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, break; case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - } else { - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - } + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1366,21 +1275,14 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { + if (type == TCG_TYPE_I64 && !sgn) { tcg_out_ext32u(s, lo, lo); } break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - } else { - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); - } + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); break; default: @@ -1416,38 +1318,6 @@ static const TCGOutOpQemuLdSt outop_qemu_ld = { .out = tgen_qemu_ld, }; -static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc = get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - ldst = prepare_host_addr(s, &h, addr, oi, true); - - if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { - tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, type); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, type); - } - - if (ldst) { - ldst->type = type; - ldst->datalo_reg = datalo; - ldst->datahi_reg = datahi; - ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); - } -} - -static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint = - TCG_TARGET_REG_BITS == 32 ? C_O2_I1(r, r, r) : C_NotImplemented, - .out = - TCG_TARGET_REG_BITS == 32 ? tgen_qemu_ld2 : NULL, -}; - static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { @@ -1462,12 +1332,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_SD, lo, base, 0); - } else { - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); - } + tcg_out_opc_imm(s, OPC_SD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1495,15 +1360,8 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, sd1, lo, base, 0); - tcg_out_opc_imm(s, sd2, lo, base, 7); - } else { - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); - } + tcg_out_opc_imm(s, sd1, lo, base, 0); + tcg_out_opc_imm(s, sd2, lo, base, 7); break; default: @@ -1539,38 +1397,6 @@ static const TCGOutOpQemuLdSt outop_qemu_st = { .out = tgen_qemu_st, }; -static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc = get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - ldst = prepare_host_addr(s, &h, addr, oi, false); - - if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { - tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); - } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); - } - - if (ldst) { - ldst->type = type; - ldst->datalo_reg = datalo; - ldst->datahi_reg = datahi; - ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); - } -} - -static const TCGOutOpQemuLdSt2 outop_qemu_st2 = { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint = - TCG_TARGET_REG_BITS == 32 ? C_O0_I3(rz, rz, r) : C_NotImplemented, - .out = - TCG_TARGET_REG_BITS == 32 ? tgen_qemu_st2 : NULL, -}; - static void tcg_out_mb(TCGContext *s, unsigned a0) { static const MIPSInsn sync[] = { @@ -1593,22 +1419,14 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) int16_t lo = 0; if (a0) { - intptr_t ofs; - if (TCG_TARGET_REG_BITS == 64) { - ofs = tcg_tbrel_diff(s, (void *)a0); - lo = ofs; - if (ofs == lo) { - base = TCG_REG_TB; - } else { - base = TCG_REG_V0; - tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); - tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); - } + intptr_t ofs = tcg_tbrel_diff(s, (void *)a0); + lo = ofs; + if (ofs == lo) { + base = TCG_REG_TB; } else { - ofs = a0; - lo = ofs; base = TCG_REG_V0; tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { @@ -1625,35 +1443,24 @@ static void tcg_out_goto_tb(TCGContext *s, int which) TCGReg base, dest; /* indirect jump method */ - if (TCG_TARGET_REG_BITS == 64) { - dest = TCG_REG_TB; - base = TCG_REG_TB; - ofs = tcg_tbrel_diff(s, (void *)ofs); - } else { - dest = TCG_TMP0; - base = TCG_REG_ZERO; - } + dest = TCG_REG_TB; + base = TCG_REG_TB; + ofs = tcg_tbrel_diff(s, (void *)ofs); tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); /* delay slot */ tcg_out_nop(s); set_jmp_reset_offset(s, which); - if (TCG_TARGET_REG_BITS == 64) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); - } + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); } static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) { tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); - } else { - tcg_out_nop(s); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } void tb_target_set_jmp_target(const TranslationBlock *tb, int n, @@ -1848,7 +1655,6 @@ static const TCGOutOpBinary outop_eqv = { .base.static_constraint = C_NotImplemented, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) { tcg_out_dsra(s, a0, a1, 32); @@ -1858,7 +1664,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = { .base.static_constraint = C_O1_I1(r, r), .out_rr = tgen_extrh_i64_i32, }; -#endif static void tgen_mul(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -2247,7 +2052,6 @@ static const TCGOutOpBswap outop_bswap32 = { .out_rr = tgen_bswap32, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { @@ -2265,7 +2069,6 @@ static const TCGOutOpUnary outop_bswap64 = { .base.static_constraint = C_O1_I1(r, r), .out_rr = tgen_bswap64, }; -#endif /* TCG_TARGET_REG_BITS == 64 */ static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -2393,7 +2196,6 @@ static const TCGOutOpLoad outop_ld16s = { .out = tgen_ld16s, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -2415,7 +2217,6 @@ static const TCGOutOpLoad outop_ld32s = { .base.static_constraint = C_O1_I1(r, r), .out = tgen_ld32s, }; -#endif static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -2586,17 +2387,15 @@ static void tcg_target_qemu_prologue(TCGContext *s) * with the address of the prologue, so we can use that instead * of TCG_REG_TB. */ -#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) +#if !defined(__mips_abicalls) # error "Unknown mips abi" #endif tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, - TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); + TCG_REG_T9); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); /* Call generated code */ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); @@ -2652,10 +2451,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* t3 = dcba -- delay slot */ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - if (TCG_TARGET_REG_BITS == 32) { - return; - } - /* * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. */ @@ -2750,9 +2545,7 @@ static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - if (TCG_TARGET_REG_BITS == 64) { - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); @@ -2783,9 +2576,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ - } + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ } typedef struct { -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (4 preceding siblings ...) 2025-08-20 14:21 ` [PATCH 5/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé @ 2025-08-21 20:48 ` Richard Henderson 5 siblings, 0 replies; 12+ messages in thread From: Richard Henderson @ 2025-08-21 20:48 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Aleksandar Rikalo, Riku Voipio, Aurelien Jarno, Alex Bennée, Paolo Bonzini, Thomas Huth, Huacai Chen, Jiaxun Yang On 8/21/25 00:21, Philippe Mathieu-Daudé wrote: > Philippe Mathieu-Daudé (5): > docker: Remove 32-bit MIPS toolchain from debian-all-test image > gitlab: Stop cross-testing for 32-bit MIPS hosts > docker: Stop building 32-bit MIPS images > tcg/mips: Check O32/N32/64 ABI definitions actually exist > tcg/mips: Remove support for 32-bit hosts Modulo the ld2/st2 thing, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-08-25 12:34 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-20 14:21 [PATCH 0/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-08-20 14:21 ` [PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé 2025-08-22 11:23 ` Alex Bennée 2025-08-22 14:49 ` Philippe Mathieu-Daudé 2025-08-20 14:21 ` [PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé 2025-08-25 12:31 ` Thomas Huth 2025-08-20 14:21 ` [PATCH 3/5] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé 2025-08-25 12:33 ` Thomas Huth 2025-08-20 14:21 ` [PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist Philippe Mathieu-Daudé 2025-08-21 21:09 ` Richard Henderson 2025-08-20 14:21 ` [PATCH 5/5] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-08-21 20:48 ` [PATCH 0/5] " Richard Henderson
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