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[2a02:3100:249c:be00:219:99ff:feb2:2458]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61a755d9cfasm4161182a12.9.2025.08.20.14.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 14:19:58 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, Bernhard Beschow , Guenter Roeck Subject: [PATCH 09/10] hw/pci-host/designware: Implement device reset Date: Wed, 20 Aug 2025 23:19:31 +0200 Message-ID: <20250820211932.27302-10-shentey@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250820211932.27302-1-shentey@gmail.com> References: <20250820211932.27302-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fixes the memory mapping to be cleared during reset, like real hardware would do. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index d71133a456..2dd4937e52 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -442,11 +442,6 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); DesignwarePCIEHost *host = designware_pcie_root_to_host(root); PCIBridge *br = PCI_BRIDGE(dev); - /* - * Dummy values used for initial configuration of MemoryRegions - * that belong to a given viewport - */ - const hwaddr dummy_offset = 0; br->bus_name = "dw-pcie"; @@ -484,6 +479,26 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) DesignwarePCIEViewport *viewport = &root->viewports[i][j]; viewport->name = names[i][j]; viewport->inbound = i == DESIGNWARE_PCIE_VIEWPORT_INBOUND; + } + } + + memory_region_init_io(&root->msi.iomem, OBJECT(root), + &designware_pci_host_msi_ops, + root, "pcie-msi", 0x4); + memory_region_add_subregion(&host->pci.memory, 0, &root->msi.iomem); +} + +static void designware_pcie_root_reset(DeviceState *dev) +{ + DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); + DesignwarePCIEViewport *viewport; + + pci_bridge_reset(dev); + + for (int i = 0; i < ARRAY_SIZE(root->viewports); i++) { + for (int j = 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { + viewport = &root->viewports[i][j]; + viewport->base = 0x0000000000000000ULL; viewport->target = 0x0000000000000000ULL; viewport->limit = UINT32_MAX; @@ -494,17 +509,13 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) } } - memory_region_init_io(&root->msi.iomem, OBJECT(root), - &designware_pci_host_msi_ops, - root, "pcie-msi", 0x4); /* * We initially place MSI interrupt I/O region at address 0 and * disable it. It'll be later moved to correct offset and enabled * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS */ - memory_region_add_subregion(&host->pci.memory, dummy_offset, - &root->msi.iomem); + memory_region_set_address(&root->msi.iomem, 0); memory_region_set_enabled(&root->msi.iomem, false); } @@ -602,7 +613,7 @@ static void designware_pcie_root_class_init(ObjectClass *klass, k->config_read = designware_pcie_root_config_read; k->config_write = designware_pcie_root_config_write; - device_class_set_legacy_reset(dc, pci_bridge_reset); + device_class_set_legacy_reset(dc, designware_pcie_root_reset); /* * PCI-facing part of the host bridge, not usable without the * host-facing part, which can't be device_add'ed, yet. -- 2.50.1