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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
	eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com,
	peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com,
	nicolinc@nvidia.com, joao.m.martins@oracle.com,
	clement.mathieu--drif@eviden.com, kevin.tian@intel.com,
	yi.l.liu@intel.com, chao.p.peng@intel.com,
	Yi Sun <yi.y.sun@linux.intel.com>,
	Zhenzhong Duan <zhenzhong.duan@intel.com>
Subject: [PATCH v5 17/21] intel_iommu: Propagate PASID-based iotlb invalidation to host
Date: Fri, 22 Aug 2025 02:40:55 -0400	[thread overview]
Message-ID: <20250822064101.123526-18-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com>

From: Yi Liu <yi.l.liu@intel.com>

This traps the guest PASID-based iotlb invalidation request and propagate it
to host.

Intel VT-d 3.0 supports nested translation in PASID granularity. Guest SVA
support could be implemented by configuring nested translation on specific
pasid. This is also known as dual stage DMA translation.

Under such configuration, guest owns the GVA->GPA translation which is
configured as stage-1 page table on host side for a specific pasid, and host
owns GPA->HPA translation. As guest owns stage-1 translation table, piotlb
invalidation should be propagated to host since host IOMMU will cache first
level page table related mappings during DMA address translation.

Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
 hw/i386/intel_iommu_internal.h |  6 +++
 hw/i386/intel_iommu.c          | 95 +++++++++++++++++++++++++++++++++-
 2 files changed, 99 insertions(+), 2 deletions(-)

diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 8af1004888..c1a9263651 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -596,6 +596,12 @@ typedef struct VTDPASIDCacheInfo {
     uint16_t devfn;
 } VTDPASIDCacheInfo;
 
+typedef struct VTDPIOTLBInvInfo {
+    uint16_t domain_id;
+    uint32_t pasid;
+    struct iommu_hwpt_vtd_s1_invalidate *inv_data;
+} VTDPIOTLBInvInfo;
+
 /* PASID Table Related Definitions */
 #define VTD_PASID_DIR_BASE_ADDR_MASK  (~0xfffULL)
 #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 6c0e502d1c..7efa22f4ec 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2611,12 +2611,99 @@ static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op,
 
     return ret;
 }
+
+static void
+vtd_invalidate_piotlb_locked(VTDAddressSpace *vtd_as,
+                             struct iommu_hwpt_vtd_s1_invalidate *cache)
+{
+    IntelIOMMUState *s = vtd_as->iommu_state;
+    VTDHostIOMMUDevice *vtd_hiod = vtd_find_hiod_iommufd(s, vtd_as);
+    HostIOMMUDeviceIOMMUFD *idev;
+    uint32_t entry_num = 1; /* Only implement one request for simplicity */
+    Error *local_err = NULL;
+
+    if (!vtd_hiod || !vtd_as->s1_hwpt) {
+        return;
+    }
+    idev = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
+
+    if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_as->s1_hwpt,
+                                          IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
+                                          sizeof(*cache), &entry_num, cache,
+                                          &local_err)) {
+        /* Something wrong in kernel, but trying to continue */
+        error_report_err(local_err);
+    }
+}
+
+/*
+ * This function is a loop function for the s->vtd_address_spaces
+ * list with VTDPIOTLBInvInfo as execution filter. It propagates
+ * the piotlb invalidation to host.
+ */
+static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value,
+                                         gpointer user_data)
+{
+    VTDPIOTLBInvInfo *piotlb_info = user_data;
+    VTDAddressSpace *vtd_as = value;
+    VTDPASIDCacheEntry *pc_entry = &vtd_as->pasid_cache_entry;
+    uint32_t pasid;
+    uint16_t did;
+
+    /* Replay only fills pasid entry cache for passthrough device */
+    if (!pc_entry->valid ||
+        !vtd_pe_pgtt_is_flt(&pc_entry->pasid_entry)) {
+        return;
+    }
+
+    if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) {
+        return;
+    }
+
+    did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry);
+
+    if (piotlb_info->domain_id == did && piotlb_info->pasid == pasid) {
+        vtd_invalidate_piotlb_locked(vtd_as, piotlb_info->inv_data);
+    }
+}
+
+static void
+vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,
+                                 uint16_t domain_id, uint32_t pasid,
+                                 hwaddr addr, uint64_t npages, bool ih)
+{
+    struct iommu_hwpt_vtd_s1_invalidate cache_info = { 0 };
+    VTDPIOTLBInvInfo piotlb_info;
+
+    cache_info.addr = addr;
+    cache_info.npages = npages;
+    cache_info.flags = ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0;
+
+    piotlb_info.domain_id = domain_id;
+    piotlb_info.pasid = pasid;
+    piotlb_info.inv_data = &cache_info;
+
+    /*
+     * Go through each vtd_as instance in s->vtd_address_spaces, find out
+     * the affected host device which need host piotlb invalidation. Piotlb
+     * invalidation should check pasid cache per architecture point of view.
+     */
+    g_hash_table_foreach(s->vtd_address_spaces,
+                         vtd_flush_host_piotlb_locked, &piotlb_info);
+}
 #else
 static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op,
                                 Error **errp)
 {
     return 0;
 }
+
+static void
+vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,
+                                 uint16_t domain_id, uint32_t pasid,
+                                 hwaddr addr, uint64_t npages, bool ih)
+{
+}
 #endif
 
 static int vtd_bind_guest_pasid_report_err(VTDAddressSpace *vtd_as,
@@ -3295,6 +3382,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
     vtd_iommu_lock(s);
     g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid,
                                 &info);
+    vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, 0, (uint64_t)-1, 0);
     vtd_iommu_unlock(s);
 
     QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
@@ -3316,7 +3404,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
 }
 
 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
-                                       uint32_t pasid, hwaddr addr, uint8_t am)
+                                       uint32_t pasid, hwaddr addr, uint8_t am,
+                                       bool ih)
 {
     VTDIOTLBPageInvInfo info;
 
@@ -3328,6 +3417,7 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
     vtd_iommu_lock(s);
     g_hash_table_foreach_remove(s->iotlb,
                                 vtd_hash_remove_by_page_piotlb, &info);
+    vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, addr, 1 << am, ih);
     vtd_iommu_unlock(s);
 
     vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid);
@@ -3359,7 +3449,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
     case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
         am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
         addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
-        vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am);
+        vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am,
+                                   VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]));
         break;
 
     default:
-- 
2.47.1



  parent reply	other threads:[~2025-08-22  6:44 UTC|newest]

Thread overview: 113+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-22  6:40 [PATCH v5 00/21] intel_iommu: Enable stage-1 translation for passthrough device Zhenzhong Duan
2025-08-22  6:40 ` [PATCH v5 01/21] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Zhenzhong Duan
2025-08-22 22:19   ` Nicolin Chen via
2025-08-25  6:01     ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 02/21] hw/pci: Introduce pci_device_get_viommu_cap() Zhenzhong Duan
2025-08-22 22:22   ` Nicolin Chen
2025-08-27 11:13   ` Yi Liu
2025-08-27 11:22     ` Eric Auger
2025-08-27 12:30       ` Yi Liu
2025-08-27 12:32         ` Eric Auger
2025-08-27 15:30           ` Nicolin Chen
2025-08-28  8:26             ` Yi Liu
2025-08-28  9:06               ` Duan, Zhenzhong
2025-08-29  1:54                 ` Duan, Zhenzhong
2025-08-29  3:26                   ` Nicolin Chen
2025-09-01  2:35                     ` Duan, Zhenzhong
2025-09-01  2:59                       ` Nicolin Chen
2025-09-01  3:31                         ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 03/21] intel_iommu: Implement get_viommu_cap() callback Zhenzhong Duan
2025-08-22 22:23   ` Nicolin Chen
2025-08-22  6:40 ` [PATCH v5 04/21] vfio: Introduce helper vfio_pci_from_vfio_device() Zhenzhong Duan
2025-08-22 22:40   ` Nicolin Chen via
2025-08-25  6:06     ` Duan, Zhenzhong
2025-08-27 11:13   ` Yi Liu
2025-08-27 11:34   ` Eric Auger
2025-09-01 16:36   ` Cédric Le Goater
2025-09-02  2:12     ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 05/21] vfio/iommufd: Force creating nested parent domain Zhenzhong Duan
2025-08-22 23:12   ` Nicolin Chen
2025-08-25  8:28     ` Duan, Zhenzhong
2025-08-27 11:51       ` Eric Auger
2025-08-27 11:48   ` Eric Auger
2025-08-28  9:53     ` Duan, Zhenzhong
2025-08-28 13:00       ` Eric Auger
2025-08-29  1:40         ` Duan, Zhenzhong
2025-08-29  3:47           ` Nicolin Chen
2025-08-22  6:40 ` [PATCH v5 06/21] hw/pci: Export pci_device_get_iommu_bus_devfn() and return bool Zhenzhong Duan
2025-08-22 23:13   ` Nicolin Chen
2025-08-27 11:14   ` Yi Liu
2025-08-22  6:40 ` [PATCH v5 07/21] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Zhenzhong Duan
2025-08-22 23:17   ` Nicolin Chen
2025-08-26 17:21   ` Nicolin Chen
2025-08-27  6:45     ` Duan, Zhenzhong
2025-08-27  8:51       ` Nicolin Chen
2025-08-27 16:36     ` Eric Auger
2025-08-27 16:57       ` Nicolin Chen
2025-08-27 11:14   ` Yi Liu
2025-08-28  9:17     ` Duan, Zhenzhong
2025-08-29  2:57       ` Yi Liu
2025-08-22  6:40 ` [PATCH v5 08/21] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Zhenzhong Duan
2025-08-27 11:42   ` Yi Liu
2025-08-28  9:37     ` Duan, Zhenzhong
2025-08-27 11:55   ` Eric Auger
2025-08-22  6:40 ` [PATCH v5 09/21] intel_iommu: Fail passthrough device under PCI bridge if x-flts=on Zhenzhong Duan
2025-08-28 10:33   ` Yi Liu
2025-09-01  5:14     ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 10/21] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Zhenzhong Duan
2025-08-28 11:36   ` Yi Liu
2025-09-01  5:33     ` Duan, Zhenzhong
2025-09-03  6:30       ` Yi Liu
2025-09-03  7:13         ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 11/21] intel_iommu: Handle PASID entry removal and update Zhenzhong Duan
2025-08-27 14:25   ` Eric Auger
2025-09-01  3:17     ` Duan, Zhenzhong
2025-08-28 12:05   ` Yi Liu
2025-09-01  3:31     ` Duan, Zhenzhong
2025-09-03  7:58       ` Yi Liu
2025-09-04  2:37         ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 12/21] intel_iommu: Handle PASID entry addition Zhenzhong Duan
2025-08-27 16:22   ` Eric Auger
2025-09-01  9:03     ` Duan, Zhenzhong
2025-09-03  8:52       ` Yi Liu
2025-09-04  2:45         ` Duan, Zhenzhong
2025-08-29  5:46   ` Yi Liu
2025-08-22  6:40 ` [PATCH v5 13/21] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Zhenzhong Duan
2025-08-27 16:28   ` Eric Auger
2025-08-29  5:56     ` Yi Liu
2025-09-01  9:04     ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 14/21] intel_iommu: Stick to system MR for IOMMUFD backed host device when x-fls=on Zhenzhong Duan
2025-08-27 17:14   ` Eric Auger
2025-08-29  6:06   ` Yi Liu
2025-08-22  6:40 ` [PATCH v5 15/21] intel_iommu: Bind/unbind guest page table to host Zhenzhong Duan
2025-08-28  8:37   ` Eric Auger
2025-08-29  7:05   ` Yi Liu
2025-08-22  6:40 ` [PATCH v5 16/21] intel_iommu: Replay pasid bindings after context cache invalidation Zhenzhong Duan
2025-08-28  9:43   ` Eric Auger
2025-08-29  7:35     ` Yi Liu
2025-09-01  8:11       ` Duan, Zhenzhong
2025-09-03 10:18         ` Yi Liu
2025-09-04  6:42           ` Duan, Zhenzhong
2025-08-22  6:40 ` Zhenzhong Duan [this message]
2025-08-28 10:00   ` [PATCH v5 17/21] intel_iommu: Propagate PASID-based iotlb invalidation to host Eric Auger
2025-08-28 12:11     ` Yi Liu
2025-09-01  8:32     ` Duan, Zhenzhong
2025-08-22  6:40 ` [PATCH v5 18/21] intel_iommu: Replay all pasid bindings when either SRTP or TE bit is changed Zhenzhong Duan
2025-08-28 10:02   ` Eric Auger
2025-08-22  6:40 ` [PATCH v5 19/21] vfio: Add a new element bypass_ro in VFIOContainerBase Zhenzhong Duan
2025-08-28 12:47   ` Eric Auger
2025-08-22  6:40 ` [PATCH v5 20/21] Workaround for ERRATA_772415_SPR17 Zhenzhong Duan
2025-08-22 23:55   ` Nicolin Chen
2025-08-25  9:21     ` Duan, Zhenzhong
2025-08-25 16:58       ` Nicolin Chen
2025-08-27  7:11         ` Duan, Zhenzhong
2025-08-27  8:42           ` Nicolin Chen
2025-08-27 11:56     ` Yi Liu
2025-08-27 15:09       ` Nicolin Chen
2025-08-29  8:16         ` Yi Liu
2025-08-29  8:54           ` Nicolin Chen
2025-08-22  6:40 ` [PATCH v5 21/21] intel_iommu: Enable host device when x-flts=on in scalable mode Zhenzhong Duan
2025-08-28 12:51   ` Eric Auger
2025-08-29  7:42   ` Yi Liu
2025-08-27 11:13 ` [PATCH v5 00/21] intel_iommu: Enable stage-1 translation for passthrough device Yi Liu
2025-08-28  5:53   ` Duan, Zhenzhong

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