From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/32] target/arm: Split out gen_wrap2_i32 helper
Date: Thu, 28 Aug 2025 12:34:08 +0100 [thread overview]
Message-ID: <20250828113430.3214314-12-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250828113430.3214314-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Wrapper to extract the low 32 bits, perform an operation,
and zero-extend back to 64 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250803014019.416797-5-richard.henderson@linaro.org
[PMM: fixed wrong output-reg argument in callsites; add comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bb92bdc296a..c0fa9a44e7a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8231,13 +8231,22 @@ static bool gen_rr(DisasContext *s, int rd, int rn, ArithOneOp fn)
return true;
}
+/*
+ * Perform 32-bit operation fn on the low half of n;
+ * the high half of the output is zeroed.
+ */
+static void gen_wrap2_i32(TCGv_i64 d, TCGv_i64 n, NeonGenOneOpFn fn)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t, n);
+ fn(t, t);
+ tcg_gen_extu_i32_i64(d, t);
+}
+
static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
- TCGv_i32 t32 = tcg_temp_new_i32();
-
- tcg_gen_extrl_i64_i32(t32, tcg_rn);
- gen_helper_rbit(t32, t32);
- tcg_gen_extu_i32_i64(tcg_rd, t32);
+ gen_wrap2_i32(tcg_rd, tcg_rn, gen_helper_rbit);
}
static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
@@ -8293,11 +8302,7 @@ static void gen_clz64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
static void gen_cls32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
- TCGv_i32 t32 = tcg_temp_new_i32();
-
- tcg_gen_extrl_i64_i32(t32, tcg_rn);
- tcg_gen_clrsb_i32(t32, t32);
- tcg_gen_extu_i32_i64(tcg_rd, t32);
+ gen_wrap2_i32(tcg_rd, tcg_rn, tcg_gen_clrsb_i32);
}
TRANS(CLZ, gen_rr, a->rd, a->rn, a->sf ? gen_clz64 : gen_clz32)
--
2.43.0
next prev parent reply other threads:[~2025-08-28 11:39 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 11:33 [PULL 00/32] target-arm queue Peter Maydell
2025-08-28 11:33 ` [PULL 01/32] target/arm: Clean up of register field definitions Peter Maydell
2025-08-28 11:33 ` [PULL 02/32] tests/functional/test_aarch64_device_passthrough: update image Peter Maydell
2025-08-28 11:34 ` [PULL 03/32] tests/functional/test_aarch64_rme: " Peter Maydell
2025-08-28 11:34 ` [PULL 04/32] target/arm: Implement FEAT_SCTLR2 and enable with -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 05/32] target/arm: Implement FEAT_TCR2 " Peter Maydell
2025-08-28 11:34 ` [PULL 06/32] hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr Peter Maydell
2025-08-28 11:34 ` [PULL 07/32] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set Peter Maydell
2025-08-28 11:34 ` [PULL 08/32] target/arm: Add feature predicate for FEAT_CSSC Peter Maydell
2025-08-28 11:34 ` [PULL 09/32] target/arm: Implement MIN/MAX (immediate) Peter Maydell
2025-08-28 11:34 ` [PULL 10/32] target/arm: Implement MIN/MAX (register) Peter Maydell
2025-08-28 11:34 ` Peter Maydell [this message]
2025-08-28 11:34 ` [PULL 12/32] target/arm: Implement CTZ, CNT, ABS Peter Maydell
2025-08-28 11:34 ` [PULL 13/32] target/arm: Enable FEAT_CSSC for -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 14/32] hw/arm: add static NVDIMMs in device tree Peter Maydell
2025-08-28 11:34 ` [PULL 15/32] scripts/kernel-doc: Avoid new Perl precedence warning Peter Maydell
2025-08-28 11:34 ` [PULL 16/32] docs/sphinx/kerneldoc.py: Handle new LINENO syntax Peter Maydell
2025-08-28 11:34 ` [PULL 17/32] tests/qtest/libqtest.h: Remove stray space from doc comment Peter Maydell
2025-08-28 11:34 ` [PULL 18/32] scripts: Import Python kerneldoc from Linux kernel Peter Maydell
2025-08-28 11:34 ` [PULL 19/32] scripts/kernel-doc: strip QEMU_ from function definitions Peter Maydell
2025-08-28 11:34 ` [PULL 20/32] scripts/kernel-doc: tweak for QEMU coding standards Peter Maydell
2025-08-28 11:34 ` [PULL 21/32] scripts/kerneldoc: Switch to the Python kernel-doc script Peter Maydell
2025-08-28 11:34 ` [PULL 22/32] scripts/kernel-doc: Delete the old Perl " Peter Maydell
2025-08-28 11:34 ` [PULL 23/32] MAINTAINERS: Put kernel-doc under the "docs build machinery" section Peter Maydell
2025-08-28 11:34 ` [PULL 24/32] target/arm: Correct condition of aa64_atomics feature function Peter Maydell
2025-08-28 11:34 ` [PULL 25/32] qemu/atomic: Finish renaming atomic128-cas.h headers Peter Maydell
2025-08-28 11:34 ` [PULL 26/32] qemu/atomic: Add atomic16 primitives for xchg, fetch_and, fetch_or Peter Maydell
2025-08-28 11:34 ` [PULL 27/32] accel/tcg: Add cpu_atomic_*_mmu for 16-byte " Peter Maydell
2025-08-28 11:34 ` [PULL 28/32] tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128 Peter Maydell
2025-08-28 11:34 ` [PULL 29/32] target/arm: Rename isar_feature_aa64_atomics Peter Maydell
2025-08-28 21:42 ` Richard Henderson
2025-08-28 11:34 ` [PULL 30/32] target/arm: Implement FEAT_LSE128 Peter Maydell
2025-08-28 11:34 ` [PULL 31/32] target/arm: Enable FEAT_LSE128 for -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 32/32] hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects Peter Maydell
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