From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/32] qemu/atomic: Add atomic16 primitives for xchg, fetch_and, fetch_or
Date: Thu, 28 Aug 2025 12:34:23 +0100 [thread overview]
Message-ID: <20250828113430.3214314-27-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250828113430.3214314-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250815122653.701782-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
host/include/aarch64/host/atomic128-cas.h.inc | 57 +++++++++++
host/include/generic/host/atomic128-cas.h.inc | 96 +++++++++++++++++++
2 files changed, 153 insertions(+)
diff --git a/host/include/aarch64/host/atomic128-cas.h.inc b/host/include/aarch64/host/atomic128-cas.h.inc
index 991da4ef543..aec27df1820 100644
--- a/host/include/aarch64/host/atomic128-cas.h.inc
+++ b/host/include/aarch64/host/atomic128-cas.h.inc
@@ -38,6 +38,63 @@ static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
return int128_make128(oldl, oldh);
}
+static inline Int128 atomic16_xchg(Int128 *ptr, Int128 new)
+{
+ uint64_t newl = int128_getlo(new), newh = int128_gethi(new);
+ uint64_t oldl, oldh;
+ uint32_t tmp;
+
+ asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t"
+ "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t"
+ "cbnz %w[tmp], 0b"
+ : [mem] "+m"(*ptr), [tmp] "=&r"(tmp),
+ [oldl] "=&r"(oldl), [oldh] "=&r"(oldh)
+ : [newl] "r"(newl), [newh] "r"(newh)
+ : "memory");
+
+ return int128_make128(oldl, oldh);
+}
+
+static inline Int128 atomic16_fetch_and(Int128 *ptr, Int128 new)
+{
+ uint64_t newl = int128_getlo(new), newh = int128_gethi(new);
+ uint64_t oldl, oldh, tmpl, tmph;
+ uint32_t tmp;
+
+ asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t"
+ "and %[tmpl], %[oldl], %[newl]\n\t"
+ "and %[tmph], %[oldh], %[newh]\n\t"
+ "stlxp %w[tmp], %[tmpl], %[tmph], %[mem]\n\t"
+ "cbnz %w[tmp], 0b"
+ : [mem] "+m"(*ptr), [tmp] "=&r"(tmp),
+ [oldl] "=&r"(oldl), [oldh] "=&r"(oldh)
+ : [newl] "r"(newl), [newh] "r"(newh),
+ [tmpl] "r"(tmpl), [tmph] "r"(tmph)
+ : "memory");
+
+ return int128_make128(oldl, oldh);
+}
+
+static inline Int128 atomic16_fetch_or(Int128 *ptr, Int128 new)
+{
+ uint64_t newl = int128_getlo(new), newh = int128_gethi(new);
+ uint64_t oldl, oldh, tmpl, tmph;
+ uint32_t tmp;
+
+ asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t"
+ "orr %[tmpl], %[oldl], %[newl]\n\t"
+ "orr %[tmph], %[oldh], %[newh]\n\t"
+ "stlxp %w[tmp], %[tmpl], %[tmph], %[mem]\n\t"
+ "cbnz %w[tmp], 0b"
+ : [mem] "+m"(*ptr), [tmp] "=&r"(tmp),
+ [oldl] "=&r"(oldl), [oldh] "=&r"(oldh)
+ : [newl] "r"(newl), [newh] "r"(newh),
+ [tmpl] "r"(tmpl), [tmph] "r"(tmph)
+ : "memory");
+
+ return int128_make128(oldl, oldh);
+}
+
# define CONFIG_CMPXCHG128 1
# define HAVE_CMPXCHG128 1
#endif
diff --git a/host/include/generic/host/atomic128-cas.h.inc b/host/include/generic/host/atomic128-cas.h.inc
index 6b40cc22710..990162c56fe 100644
--- a/host/include/generic/host/atomic128-cas.h.inc
+++ b/host/include/generic/host/atomic128-cas.h.inc
@@ -23,6 +23,51 @@ atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
return r.s;
}
+
+/*
+ * Since we're looping anyway, use weak compare and swap.
+ * If the host supports weak, this will eliminate a second loop hidden
+ * within the atomic operation itself; otherwise the weak parameter is
+ * ignored.
+ */
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_xchg(Int128 *ptr, Int128 new)
+{
+ __int128_t *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128 old = *ptr_align;
+
+ while (!__atomic_compare_exchange_n(ptr_align, &old, new, true,
+ __ATOMIC_SEQ_CST, 0)) {
+ continue;
+ }
+ return old;
+}
+
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_fetch_and(Int128 *ptr, Int128 val)
+{
+ __int128_t *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128 old = *ptr_align;
+
+ while (!__atomic_compare_exchange_n(ptr_align, &old, old & val, true,
+ __ATOMIC_SEQ_CST, 0)) {
+ continue;
+ }
+ return old;
+}
+
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_fetch_or(Int128 *ptr, Int128 val)
+{
+ __int128_t *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128 old = *ptr_align;
+
+ while (!__atomic_compare_exchange_n(ptr_align, &old, old | val, true,
+ __ATOMIC_SEQ_CST, 0)) {
+ continue;
+ }
+ return old;
+}
# define HAVE_CMPXCHG128 1
#elif defined(CONFIG_CMPXCHG128)
static inline Int128 ATTRIBUTE_ATOMIC128_OPT
@@ -36,6 +81,57 @@ atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
r.i = __sync_val_compare_and_swap_16(ptr_align, c.i, n.i);
return r.s;
}
+
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_xchg(Int128 *ptr, Int128 new)
+{
+ Int128Aligned *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128Alias o, n;
+
+ n.s = new;
+ o.s = *ptr_align;
+ while (1) {
+ __int128 c = __sync_val_compare_and_swap_16(ptr_align, o.i, n.i);
+ if (c == o.i) {
+ return o.s;
+ }
+ o.i = c;
+ }
+}
+
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_fetch_and(Int128 *ptr, Int128 val)
+{
+ Int128Aligned *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128Alias o, v;
+
+ v.s = val;
+ o.s = *ptr_align;
+ while (1) {
+ __int128 c = __sync_val_compare_and_swap_16(ptr_align, o.i, o.i & v.i);
+ if (c == o.i) {
+ return o.s;
+ }
+ o.i = c;
+ }
+}
+
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+atomic16_fetch_or(Int128 *ptr, Int128 val)
+{
+ Int128Aligned *ptr_align = __builtin_assume_aligned(ptr, 16);
+ Int128Alias o, v;
+
+ v.s = val;
+ o.s = *ptr_align;
+ while (1) {
+ __int128 c = __sync_val_compare_and_swap_16(ptr_align, o.i, o.i | v.i);
+ if (c == o.i) {
+ return o.s;
+ }
+ o.i = c;
+ }
+}
# define HAVE_CMPXCHG128 1
#else
/* Fallback definition that must be optimized away, or error. */
--
2.43.0
next prev parent reply other threads:[~2025-08-28 11:37 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 11:33 [PULL 00/32] target-arm queue Peter Maydell
2025-08-28 11:33 ` [PULL 01/32] target/arm: Clean up of register field definitions Peter Maydell
2025-08-28 11:33 ` [PULL 02/32] tests/functional/test_aarch64_device_passthrough: update image Peter Maydell
2025-08-28 11:34 ` [PULL 03/32] tests/functional/test_aarch64_rme: " Peter Maydell
2025-08-28 11:34 ` [PULL 04/32] target/arm: Implement FEAT_SCTLR2 and enable with -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 05/32] target/arm: Implement FEAT_TCR2 " Peter Maydell
2025-08-28 11:34 ` [PULL 06/32] hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr Peter Maydell
2025-08-28 11:34 ` [PULL 07/32] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set Peter Maydell
2025-08-28 11:34 ` [PULL 08/32] target/arm: Add feature predicate for FEAT_CSSC Peter Maydell
2025-08-28 11:34 ` [PULL 09/32] target/arm: Implement MIN/MAX (immediate) Peter Maydell
2025-08-28 11:34 ` [PULL 10/32] target/arm: Implement MIN/MAX (register) Peter Maydell
2025-08-28 11:34 ` [PULL 11/32] target/arm: Split out gen_wrap2_i32 helper Peter Maydell
2025-08-28 11:34 ` [PULL 12/32] target/arm: Implement CTZ, CNT, ABS Peter Maydell
2025-08-28 11:34 ` [PULL 13/32] target/arm: Enable FEAT_CSSC for -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 14/32] hw/arm: add static NVDIMMs in device tree Peter Maydell
2025-08-28 11:34 ` [PULL 15/32] scripts/kernel-doc: Avoid new Perl precedence warning Peter Maydell
2025-08-28 11:34 ` [PULL 16/32] docs/sphinx/kerneldoc.py: Handle new LINENO syntax Peter Maydell
2025-08-28 11:34 ` [PULL 17/32] tests/qtest/libqtest.h: Remove stray space from doc comment Peter Maydell
2025-08-28 11:34 ` [PULL 18/32] scripts: Import Python kerneldoc from Linux kernel Peter Maydell
2025-08-28 11:34 ` [PULL 19/32] scripts/kernel-doc: strip QEMU_ from function definitions Peter Maydell
2025-08-28 11:34 ` [PULL 20/32] scripts/kernel-doc: tweak for QEMU coding standards Peter Maydell
2025-08-28 11:34 ` [PULL 21/32] scripts/kerneldoc: Switch to the Python kernel-doc script Peter Maydell
2025-08-28 11:34 ` [PULL 22/32] scripts/kernel-doc: Delete the old Perl " Peter Maydell
2025-08-28 11:34 ` [PULL 23/32] MAINTAINERS: Put kernel-doc under the "docs build machinery" section Peter Maydell
2025-08-28 11:34 ` [PULL 24/32] target/arm: Correct condition of aa64_atomics feature function Peter Maydell
2025-08-28 11:34 ` [PULL 25/32] qemu/atomic: Finish renaming atomic128-cas.h headers Peter Maydell
2025-08-28 11:34 ` Peter Maydell [this message]
2025-08-28 11:34 ` [PULL 27/32] accel/tcg: Add cpu_atomic_*_mmu for 16-byte xchg, fetch_and, fetch_or Peter Maydell
2025-08-28 11:34 ` [PULL 28/32] tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128 Peter Maydell
2025-08-28 11:34 ` [PULL 29/32] target/arm: Rename isar_feature_aa64_atomics Peter Maydell
2025-08-28 21:42 ` Richard Henderson
2025-08-28 11:34 ` [PULL 30/32] target/arm: Implement FEAT_LSE128 Peter Maydell
2025-08-28 11:34 ` [PULL 31/32] target/arm: Enable FEAT_LSE128 for -cpu max Peter Maydell
2025-08-28 11:34 ` [PULL 32/32] hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects Peter Maydell
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