From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.caveayland@nutanix.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 11/28] hw/i386/pc_piix.c: simplify RAM size logic in pc_init_isa()
Date: Fri, 29 Aug 2025 14:59:18 +0200 [thread overview]
Message-ID: <20250829125935.1526984-12-pbonzini@redhat.com> (raw)
In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com>
From: Mark Cave-Ayland <mark.caveayland@nutanix.com>
All isapc machines must have 32-bit CPUs and so the RAM split logic can be hardcoded
accordingly.
Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250828111057.468712-12-mark.caveayland@nutanix.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_piix.c | 58 ++++-------------------------------------------
1 file changed, 4 insertions(+), 54 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index daf63a326b6..0bc033943ca 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -445,7 +445,6 @@ static void pc_init_isa(MachineState *machine)
GSIState *gsi_state;
MemoryRegion *ram_memory;
MemoryRegion *rom_memory = system_memory;
- ram_addr_t lowmem;
uint64_t hole64_size = 0;
/*
@@ -480,65 +479,16 @@ static void pc_init_isa(MachineState *machine)
}
/*
- * Calculate ram split, for memory below and above 4G. It's a bit
- * complicated for backward compatibility reasons ...
- *
- * - Traditional split is 3.5G (lowmem = 0xe0000000). This is the
- * default value for max_ram_below_4g now.
- *
- * - Then, to gigabyte align the memory, we move the split to 3G
- * (lowmem = 0xc0000000). But only in case we have to split in
- * the first place, i.e. ram_size is larger than (traditional)
- * lowmem. And for new machine types (gigabyte_align = true)
- * only, for live migration compatibility reasons.
- *
- * - Next the max-ram-below-4g option was added, which allowed to
- * reduce lowmem to a smaller value, to allow a larger PCI I/O
- * window below 4G. qemu doesn't enforce gigabyte alignment here,
- * but prints a warning.
- *
- * - Finally max-ram-below-4g got updated to also allow raising lowmem,
- * so legacy non-PAE guests can get as much memory as possible in
- * the 32bit address space below 4G.
- *
- * - Note that Xen has its own ram setup code in xen_ram_init(),
- * called via xen_hvm_init_pc().
- *
- * Examples:
- * qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high
- * qemu -M pc -m 4G (new default) -> 3072M low, 1024M high
- * qemu -M pc,max-ram-below-4g=2G -m 4G -> 2048M low, 2048M high
- * qemu -M pc,max-ram-below-4g=4G -m 3968M -> 3968M low (=4G-128M)
+ * There is no RAM split for the isapc machine
*/
if (xen_enabled()) {
xen_hvm_init_pc(pcms, &ram_memory);
} else {
ram_memory = machine->ram;
- if (!pcms->max_ram_below_4g) {
- pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */
- }
- lowmem = pcms->max_ram_below_4g;
- if (machine->ram_size >= pcms->max_ram_below_4g) {
- if (pcmc->gigabyte_align) {
- if (lowmem > 0xc0000000) {
- lowmem = 0xc0000000;
- }
- if (lowmem & (1 * GiB - 1)) {
- warn_report("Large machine and max_ram_below_4g "
- "(%" PRIu64 ") not a multiple of 1G; "
- "possible bad performance.",
- pcms->max_ram_below_4g);
- }
- }
- }
- if (machine->ram_size >= lowmem) {
- x86ms->above_4g_mem_size = machine->ram_size - lowmem;
- x86ms->below_4g_mem_size = lowmem;
- } else {
- x86ms->above_4g_mem_size = 0;
- x86ms->below_4g_mem_size = machine->ram_size;
- }
+ pcms->max_ram_below_4g = 3.5 * GiB;
+ x86ms->above_4g_mem_size = 0;
+ x86ms->below_4g_mem_size = machine->ram_size;
}
x86_cpus_init(x86ms, pcmc->default_cpu_version);
--
2.51.0
next prev parent reply other threads:[~2025-08-30 15:44 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 12:59 [PULL 00/28] i386, accel, memory patches for 2025-08-29 Paolo Bonzini
2025-08-29 12:59 ` [PULL 01/28] hw/i386/pc_piix.c: restrict isapc machine to 32-bit CPUs Paolo Bonzini
2025-08-29 12:59 ` [PULL 02/28] hw/i386/pc_piix.c: restrict isapc machine to 3.5G memory Paolo Bonzini
2025-08-29 12:59 ` [PULL 03/28] hw/i386/pc_piix.c: remove include for loader.h Paolo Bonzini
2025-08-29 12:59 ` [PULL 04/28] hw/i386/pc_piix.c: inline pc_xen_hvm_init_pci() into pc_xen_hvm_init() Paolo Bonzini
2025-08-29 12:59 ` [PULL 05/28] hw/i386/pc_piix.c: duplicate pc_init1() into pc_isa_init() Paolo Bonzini
2025-08-29 12:59 ` [PULL 06/28] hw/i386/pc_piix.c: remove pcmc->pci_enabled dependent initialisation from pc_init_isa() Paolo Bonzini
2025-08-29 12:59 ` [PULL 07/28] hw/i386/pc_piix.c: remove igvm " Paolo Bonzini
2025-08-29 12:59 ` [PULL 08/28] hw/i386/pc_piix.c: remove SMI and piix4_pm " Paolo Bonzini
2025-08-29 12:59 ` [PULL 09/28] hw/i386/pc_piix.c: remove SGX " Paolo Bonzini
2025-08-29 12:59 ` [PULL 10/28] hw/i386/pc_piix.c: remove nvdimm " Paolo Bonzini
2025-08-29 12:59 ` Paolo Bonzini [this message]
2025-08-29 12:59 ` [PULL 12/28] hw/i386/pc_piix.c: hardcode hole64_size to 0 in pc_init_isa() Paolo Bonzini
2025-08-29 12:59 ` [PULL 13/28] hw/i386/pc_piix.c: remove pc_system_flash_cleanup_unused() from pc_init_isa() Paolo Bonzini
2025-08-29 12:59 ` [PULL 14/28] hw/i386/pc_piix.c: always initialise ISA IDE drives in pc_init_isa() Paolo Bonzini
2025-08-29 12:59 ` [PULL 15/28] hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1() Paolo Bonzini
2025-09-01 10:43 ` Peter Maydell
2025-09-01 13:27 ` Mark Cave-Ayland
2025-08-29 12:59 ` [PULL 16/28] hw/i386: move isapc machine to separate isapc.c file Paolo Bonzini
2025-08-29 12:59 ` [PULL 17/28] hw/i386/pc_piix.c: remove unused headers after isapc machine split Paolo Bonzini
2025-08-29 12:59 ` [PULL 18/28] hw/i386/pc_piix.c: replace rom_memory with pci_memory Paolo Bonzini
2025-08-29 12:59 ` [PULL 19/28] hw/i386/isapc.c: replace rom_memory with system_memory Paolo Bonzini
2025-08-29 12:59 ` [PULL 20/28] user-exec: ensure interrupt_request is not used Paolo Bonzini
2025-08-29 12:59 ` [PULL 21/28] add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide Paolo Bonzini
2025-10-27 14:38 ` Thomas Huth
2025-08-29 12:59 ` [PULL 22/28] memory: reintroduce BQL-free fine-grained PIO/MMIO Paolo Bonzini
2025-08-29 12:59 ` [PULL 23/28] acpi: mark PMTIMER as unlocked Paolo Bonzini
2025-08-29 12:59 ` [PULL 24/28] hpet: switch to fine-grained device locking Paolo Bonzini
2025-09-08 14:30 ` Daniel P. Berrangé
2025-09-10 11:16 ` Igor Mammedov
2025-09-10 11:23 ` Paolo Bonzini
2025-09-10 12:56 ` Igor Mammedov
2025-09-15 13:26 ` Peter Maydell
2025-09-10 14:25 ` [PATCH] hpet: guard IRQ handling with BQL Igor Mammedov
2025-09-11 13:40 ` Paolo Bonzini
2025-08-29 12:59 ` [PULL 25/28] hpet: move out main counter read into a separate block Paolo Bonzini
2025-08-29 12:59 ` [PULL 26/28] hpet: make main counter read lock-less Paolo Bonzini
2025-08-29 12:59 ` [PULL 27/28] kvm: i386: irqchip: take BQL only if there is an interrupt Paolo Bonzini
2025-08-29 12:59 ` [PULL 28/28] tcg: move interrupt caching and single step masking closer to user Paolo Bonzini
2025-08-31 7:28 ` [PULL 00/28] i386, accel, memory patches for 2025-08-29 Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250829125935.1526984-12-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=mark.caveayland@nutanix.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).