From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH v2 2/5] tcg/i386: Expand sari of bits-1 as pcmpgt
Date: Sat, 30 Aug 2025 13:39:23 +1000 [thread overview]
Message-ID: <20250830033926.372955-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250830033926.372955-1-richard.henderson@linaro.org>
Expand arithmetic right shift of bits-1 as a comparison vs 0.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 088c6c9264..4cd5d4276c 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -4357,6 +4357,12 @@ static void expand_vec_sari(TCGType type, unsigned vece,
{
TCGv_vec t1, t2;
+ if (imm >= (8 << vece) - 1) {
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, v0, v1,
+ tcg_constant_vec(type, MO_64, 0));
+ return;
+ }
+
switch (vece) {
case MO_8:
/* Unpack to 16-bit, shift, and repack. */
--
2.43.0
next prev parent reply other threads:[~2025-08-30 16:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-30 3:39 [PATCH v2 0/5] tcg/i386: Improve vector shifts Richard Henderson
2025-08-30 3:39 ` [PATCH v2 1/5] cpuinfo/i386: Detect GFNI as an AVX extension Richard Henderson
2025-08-30 3:39 ` Richard Henderson [this message]
2025-08-30 3:39 ` [PATCH v2 3/5] tcg/i386: Use canonical operand ordering in expand_vec_sari Richard Henderson
2025-09-01 6:44 ` Philippe Mathieu-Daudé
2025-09-02 13:28 ` Richard Henderson
2025-08-30 3:39 ` [PATCH v2 4/5] tcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vec Richard Henderson
2025-08-30 3:39 ` [PATCH v2 5/5] tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts Richard Henderson
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