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[122.150.204.48]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4d96829a66sm2435905a12.6.2025.08.29.22.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:41:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 00/84] target/arm: Implement FEAT_GCS Date: Sat, 30 Aug 2025 15:40:04 +1000 Message-ID: <20250830054128.448363-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on Peter's tags/pull-target-arm-20250828. Tree: https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-gcs This includes the prerequisite features, ATS1A and S1PIE, and not a prerequisite but closely related, S2PIE. This passes the linux kselftests for gcs, with a 48-bit VA. I also include a few smoke tests in tests/tcg/. This includes a best-effort linux-user implementation. Since we don't have softmmu in user-only (yet), gcs stack pages get normal read/write access. This means we cannot write-protect the pages in the same way the system implementation can. But all of the other parts of GCS work fine, which is good enough for testing. Changes for v4: - Rebase on target-arm.next, which includes all prereqs. - Fixes up the minor conflicts with the elfload.c split. - Include Thiago's t-b on the system-mode enable patch. r~ Richard Henderson (84): linux-user/aarch64: Split out signal_for_exception linux-user/aarch64: Check syndrome for EXCP_UDEF linux-user/aarch64: Generate ESR signal records target/arm: Add prot_check parameter to pmsav8_mpu_lookup target/arm: Add in_prot_check to S1Translate target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug target/arm: Introduce get_phys_addr_for_at target/arm: Skip AF and DB updates for AccessType_AT target/arm: Add prot_check parameter to do_ats_write target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5 target/arm: Remove outdated comment for ZCR_EL12 target/arm: Implement FEAT_ATS1A target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE target/arm: Enable TCR2_ELx.PIE target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers target/arm: Force HPD for stage2 translations target/arm: Cache NV1 early in get_phys_addr_lpae target/arm: Populate PIE in aa64_va_parameters target/arm: Implement get_S1prot_indirect target/arm: Implement get_S2prot_indirect target/arm: Do not migrate env->exception target/arm: Expand CPUARMState.exception.syndrome to 64 bits target/arm: Expand syndrome parameter to raise_exception* target/arm: Implement dirtybit check for PIE target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max include/hw/core/cpu: Introduce MMUIdxMap include/hw/core/cpu: Introduce cpu_tlb_fast include/hw/core/cpu: Invert the indexing into CPUTLBDescFast target/hppa: Adjust mmu indexes to begin with 0 include/exec/memopidx: Adjust for 32 mmu indexes include/hw/core/cpu: Widen MMUIdxMap target/arm: Split out mmuidx.h from cpu.h target/arm: Convert arm_mmu_idx_to_el from switch to table target/arm: Remove unused env argument from regime_el target/arm: Convert regime_el from switch to table target/arm: Convert regime_has_2_ranges from switch to table target/arm: Remove unused env argument from regime_is_pan target/arm: Convert regime_is_pan from switch to table target/arm: Remove unused env argument from regime_is_user target/arm: Convert regime_is_user from switch to table target/arm: Convert arm_mmu_idx_is_stage1_of_2 from switch to table target/arm: Convert regime_is_stage2 to table target/arm: Introduce mmu indexes for GCS target/arm: Introduce regime_to_gcs target/arm: Support page protections for GCS mmu indexes target/arm: Implement gcs bit for data abort target/arm: Add GCS cpregs target/arm: Add GCS enable and trap levels to DisasContext target/arm: Implement FEAT_CHK target/arm: Expand pstate to 64 bits target/arm: Add syndrome data for EC_GCS target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx target/arm: Split {arm,core}_user_mem_index target/arm: Introduce delay_exception{_el} target/arm: Emit HSTR trap exception out of line target/arm: Emit v7m LTPSIZE exception out of line target/arm: Implement GCSSTR, GCSSTTR target/arm: Implement GCSB target/arm: Implement GCSPUSHM target/arm: Implement GCSPOPM target/arm: Implement GCSPUSHX target/arm: Implement GCSPOPX target/arm: Implement GCSPOPCX target/arm: Implement GCSSS1 target/arm: Implement GCSSS2 target/arm: Add gcs record for BL target/arm: Add gcs record for BLR target/arm: Add gcs record for BLR with PAuth target/arm: Load gcs record for RET target/arm: Load gcs record for RET with PAuth target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL target/arm: Implement EXLOCK check during exception return target/arm: Enable FEAT_GCS with -cpu max linux-user/aarch64: Implement prctls for GCS linux-user/aarch64: Allocate new gcs stack on clone linux-user/aarch64: Release gcs stack on thread exit linux-user/aarch64: Implement map_shadow_stack syscall target/arm: Enable GCSPR_EL0 for read in user-mode linux-user/aarch64: Inject SIGSEGV for GCS faults linux-user/aarch64: Generate GCS signal records linux-user/aarch64: Enable GCS in HWCAP tests/tcg/aarch64: Add gcsstr tests/tcg/aarch64: Add gcspushm tests/tcg/aarch64: Add gcsss include/exec/cputlb.h | 32 +-- include/exec/memopidx.h | 9 +- include/hw/core/cpu.h | 25 +- linux-user/aarch64/gcs-internal.h | 38 +++ linux-user/aarch64/target_prctl.h | 96 +++++++ linux-user/aarch64/target_signal.h | 1 + linux-user/qemu.h | 5 + target/arm/cpregs.h | 46 ++- target/arm/cpu-features.h | 20 ++ target/arm/cpu.h | 242 ++-------------- target/arm/internals.h | 169 ++---------- target/arm/mmuidx-internal.h | 113 ++++++++ target/arm/mmuidx.h | 241 ++++++++++++++++ target/arm/syndrome.h | 35 +++ target/arm/tcg/translate.h | 46 ++- target/hppa/cpu.h | 28 +- tests/tcg/aarch64/gcs.h | 80 ++++++ accel/tcg/cputlb.c | 49 ++-- linux-user/aarch64/cpu_loop.c | 167 ++++++++--- linux-user/aarch64/elfload.c | 1 + linux-user/aarch64/signal.c | 170 +++++++++++- linux-user/syscall.c | 114 ++++++++ target/arm/cpregs-gcs.c | 152 ++++++++++ target/arm/cpu.c | 17 +- target/arm/gdbstub64.c | 2 + target/arm/helper.c | 268 ++++++++++++++---- target/arm/machine.c | 62 ++++- target/arm/mmuidx.c | 66 +++++ target/arm/ptw.c | 429 +++++++++++++++++++++------- target/arm/tcg-stubs.c | 2 +- target/arm/tcg/cpregs-at.c | 69 +++-- target/arm/tcg/cpu64.c | 4 + target/arm/tcg/helper-a64.c | 13 +- target/arm/tcg/hflags.c | 38 +++ target/arm/tcg/m_helper.c | 4 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/op_helper.c | 8 +- target/arm/tcg/tlb-insns.c | 47 +++- target/arm/tcg/tlb_helper.c | 18 +- target/arm/tcg/translate-a64.c | 430 ++++++++++++++++++++++++++--- target/arm/tcg/translate.c | 78 ++++-- tcg/tcg.c | 3 +- tests/tcg/aarch64/gcspushm.c | 71 +++++ tests/tcg/aarch64/gcsss.c | 74 +++++ tests/tcg/aarch64/gcsstr.c | 48 ++++ docs/system/arm/emulation.rst | 5 + target/arm/meson.build | 9 +- target/arm/tcg/a64.decode | 5 + tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tests/tcg/aarch64/Makefile.target | 5 + 51 files changed, 2931 insertions(+), 729 deletions(-) create mode 100644 linux-user/aarch64/gcs-internal.h create mode 100644 target/arm/mmuidx-internal.h create mode 100644 target/arm/mmuidx.h create mode 100644 tests/tcg/aarch64/gcs.h create mode 100644 target/arm/cpregs-gcs.c create mode 100644 target/arm/mmuidx.c create mode 100644 tests/tcg/aarch64/gcspushm.c create mode 100644 tests/tcg/aarch64/gcsss.c create mode 100644 tests/tcg/aarch64/gcsstr.c -- 2.43.0