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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Max Chou <max.chou@sifive.com>
Subject: [RFC PATCH 3/3] target/riscv: Expose Zvqdotq extension as a cpu property
Date: Mon,  1 Sep 2025 21:38:15 +0800	[thread overview]
Message-ID: <20250901133815.1693077-4-max.chou@sifive.com> (raw)
In-Reply-To: <20250901133815.1693077-1-max.chou@sifive.com>

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 95edd02e683..ed486113ba1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1373,6 +1373,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 /* These are experimental so mark with 'x-' */
 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
+    MULTI_EXT_CFG_BOOL("x-zvqdotq", ext_zvqdotq, false),
 
     { },
 };
-- 
2.43.0



      parent reply	other threads:[~2025-09-01 13:40 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-01 13:38 [RFC PATCH 0/3] Support RISC-V Zvqdotq vector dot-product extension Max Chou
2025-09-01 13:38 ` [RFC PATCH 1/3] target/riscv: Add Zvqdotq cfg property Max Chou
2025-09-01 13:38 ` [RFC PATCH 2/3] target/riscv: rvv: Add Zvqdotq support Max Chou
2025-09-02 13:38   ` Richard Henderson
2025-09-03  0:26     ` Max Chou
2025-09-03  3:43       ` Richard Henderson
2025-09-03 12:43         ` Max Chou
2025-09-01 13:38 ` Max Chou [this message]

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