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x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, 29 Aug 2025 17:31:03 +0200 Paolo Bonzini wrote: beside nit below Reviewed-by: Igor Mammedov > --- > accel/tcg/cpu-exec.c | 6 +++--- > hw/core/cpu-system.c | 2 +- > target/avr/helper.c | 4 ++-- > target/i386/hvf/x86hvf.c | 8 ++++---- > target/i386/kvm/kvm.c | 14 +++++++------- > target/i386/nvmm/nvmm-all.c | 10 +++++----- > target/i386/tcg/system/seg_helper.c | 13 ++++++------- > target/i386/tcg/system/svm_helper.c | 2 +- > target/i386/whpx/whpx-all.c | 12 ++++++------ > target/openrisc/sys_helper.c | 2 +- > target/rx/helper.c | 4 ++-- > target/s390x/tcg/excp_helper.c | 2 +- > 12 files changed, 39 insertions(+), 40 deletions(-) > > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index 8491e5badd1..508d2d2d9e2 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -784,7 +784,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, > if (unlikely(cpu_test_interrupt(cpu, ~0))) { > bql_lock(); > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_DEBUG)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_DEBUG); > cpu->exception_index = EXCP_DEBUG; > bql_unlock(); > return true; > @@ -793,7 +793,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, > /* Do nothing */ > } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HALT)) { > replay_interrupt(); > - cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); > cpu->halted = 1; > cpu->exception_index = EXCP_HLT; > bql_unlock(); > @@ -840,7 +840,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, > } > } > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_EXITTB)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_EXITTB); > /* ensure that no TB jump will be modified as > the program flow was changed */ > *last_tb = NULL; > diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c > index a975405d3a0..09c928c1f92 100644 > --- a/hw/core/cpu-system.c > +++ b/hw/core/cpu-system.c > @@ -204,7 +204,7 @@ static int cpu_common_post_load(void *opaque, int version_id) > * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the > * version_id is increased. > */ > - cpu->interrupt_request &= ~0x01; > + cpu_reset_interrupt(cpu, 0x01); > > tlb_flush(cpu); > > diff --git a/target/avr/helper.c b/target/avr/helper.c > index b9cd6d5ef27..4b29ab35263 100644 > --- a/target/avr/helper.c > +++ b/target/avr/helper.c > @@ -47,7 +47,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > cs->exception_index = EXCP_RESET; > avr_cpu_do_interrupt(cs); > > - cs->interrupt_request &= ~CPU_INTERRUPT_RESET; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_RESET); > return true; > } > } > @@ -59,7 +59,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > > env->intsrc &= env->intsrc - 1; /* clear the interrupt */ > if (!env->intsrc) { > - cs->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > } > return true; > } > diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c > index 9e05e0e5765..a502437c303 100644 > --- a/target/i386/hvf/x86hvf.c > +++ b/target/i386/hvf/x86hvf.c > @@ -397,7 +397,7 @@ bool hvf_inject_interrupts(CPUState *cs) > > if (cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { > if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_NMI; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); > info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; > wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info); > } else { > @@ -409,7 +409,7 @@ bool hvf_inject_interrupts(CPUState *cs) > cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && > (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { > int line = cpu_get_pic_interrupt(env); > - cs->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > if (line >= 0) { > wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line | > VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); > @@ -437,7 +437,7 @@ int hvf_process_events(CPUState *cs) > } > > if (cpu_test_interrupt(cs, CPU_INTERRUPT_POLL)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_POLL; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); > apic_poll_irq(cpu->apic_state); > } > if ((cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && > @@ -450,7 +450,7 @@ int hvf_process_events(CPUState *cs) > do_cpu_sipi(cpu); > } > if (cpu_test_interrupt(cs, CPU_INTERRUPT_TPR)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_TPR; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_TPR); > cpu_synchronize_state(cs); > apic_handle_tpr_access_report(cpu->apic_state, env->eip, > env->tpr_access_type); > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > index 306430a0521..8420c4090ef 100644 > --- a/target/i386/kvm/kvm.c > +++ b/target/i386/kvm/kvm.c > @@ -5066,7 +5066,7 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level) > */ > events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; > events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; > - cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); > + cpu_reset_interrupt(cs, CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); this was called without BQL in kvm_cpu_exec(), perhaps mention in commit message that beside replacing open coded interrupt reset commit also fixes potential bug since cpu_reset_interrupt() would take BQL now. (or make this hunk a separate patch) not sure but perhaps the same applies to hunk in target/i386/tcg/system/svm_helper.c > } else { > /* Keep these in cs->interrupt_request. */ > events.smi.pending = 0; > @@ -5456,7 +5456,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { > bql_lock(); > - cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); > bql_unlock(); > DPRINTF("injected NMI\n"); > ret = kvm_vcpu_ioctl(cpu, KVM_NMI); > @@ -5467,7 +5467,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) > } > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { > bql_lock(); > - cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); > bql_unlock(); > DPRINTF("injected SMI\n"); > ret = kvm_vcpu_ioctl(cpu, KVM_SMI); > @@ -5502,7 +5502,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) > > bql_lock(); > > - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); > irq = cpu_get_pic_interrupt(env); > if (irq >= 0) { > struct kvm_interrupt intr; > @@ -5597,7 +5597,7 @@ int kvm_arch_process_async_events(CPUState *cs) > /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ > assert(env->mcg_cap); > > - cs->interrupt_request &= ~CPU_INTERRUPT_MCE; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_MCE); > > kvm_cpu_synchronize_state(cs); > > @@ -5627,7 +5627,7 @@ int kvm_arch_process_async_events(CPUState *cs) > } > > if (cpu_test_interrupt(cs, CPU_INTERRUPT_POLL)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_POLL; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); > apic_poll_irq(cpu->apic_state); > } > if ((cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && > @@ -5640,7 +5640,7 @@ int kvm_arch_process_async_events(CPUState *cs) > do_cpu_sipi(cpu); > } > if (cpu_test_interrupt(cs, CPU_INTERRUPT_TPR)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_TPR; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_TPR); > kvm_cpu_synchronize_state(cs); > apic_handle_tpr_access_report(cpu->apic_state, env->eip, > env->tpr_access_type); > diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c > index c1ac74c4f04..e1151b04c6e 100644 > --- a/target/i386/nvmm/nvmm-all.c > +++ b/target/i386/nvmm/nvmm-all.c > @@ -419,7 +419,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) > > if (!has_event && cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { > if (nvmm_can_take_nmi(cpu)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); > event->type = NVMM_VCPU_EVENT_INTR; > event->vector = 2; > has_event = true; > @@ -428,7 +428,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) > > if (!has_event && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { > if (nvmm_can_take_int(cpu)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); > event->type = NVMM_VCPU_EVENT_INTR; > event->vector = cpu_get_pic_interrupt(env); > has_event = true; > @@ -437,7 +437,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) > > /* Don't want SMIs. */ > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); > } > > if (sync_tpr) { > @@ -697,7 +697,7 @@ nvmm_vcpu_loop(CPUState *cpu) > /* set int/nmi windows back to the reset state */ > } > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); > apic_poll_irq(x86_cpu->apic_state); > } > if ((cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && > @@ -710,7 +710,7 @@ nvmm_vcpu_loop(CPUState *cpu) > do_cpu_sipi(x86_cpu); > } > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_TPR; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_TPR); > nvmm_cpu_synchronize_state(cpu); > apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, > env->tpr_access_type); > diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/seg_helper.c > index 794a23ddfc4..38072e51d72 100644 > --- a/target/i386/tcg/system/seg_helper.c > +++ b/target/i386/tcg/system/seg_helper.c > @@ -178,7 +178,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > */ > switch (interrupt_request) { > case CPU_INTERRUPT_POLL: > - cs->interrupt_request &= ~CPU_INTERRUPT_POLL; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); > apic_poll_irq(cpu->apic_state); > break; > case CPU_INTERRUPT_SIPI: > @@ -186,23 +186,22 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > break; > case CPU_INTERRUPT_SMI: > cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); > - cs->interrupt_request &= ~CPU_INTERRUPT_SMI; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_SMI); > do_smm_enter(cpu); > break; > case CPU_INTERRUPT_NMI: > cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); > - cs->interrupt_request &= ~CPU_INTERRUPT_NMI; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); > env->hflags2 |= HF2_NMI_MASK; > do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); > break; > case CPU_INTERRUPT_MCE: > - cs->interrupt_request &= ~CPU_INTERRUPT_MCE; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_MCE); > do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); > break; > case CPU_INTERRUPT_HARD: > cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); > - cs->interrupt_request &= ~(CPU_INTERRUPT_HARD | > - CPU_INTERRUPT_VIRQ); > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); > intno = cpu_get_pic_interrupt(env); > qemu_log_mask(CPU_LOG_INT, > "Servicing hardware INT=0x%02x\n", intno); > @@ -215,7 +214,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > qemu_log_mask(CPU_LOG_INT, > "Servicing virtual hardware INT=0x%02x\n", intno); > do_interrupt_x86_hardirq(env, intno, 1); > - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); > env->int_ctl &= ~V_IRQ_MASK; > break; > } > diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c > index 3569196bdda..505788b0e26 100644 > --- a/target/i386/tcg/system/svm_helper.c > +++ b/target/i386/tcg/system/svm_helper.c > @@ -824,7 +824,7 @@ void do_vmexit(CPUX86State *env) > env->intercept_exceptions = 0; > > /* Clears the V_IRQ and V_INTR_MASKING bits inside the processor. */ > - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); > env->int_ctl = 0; > > /* Clears the TSC_OFFSET inside the processor. */ > diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c > index 878cdd1668c..c09a0a64f22 100644 > --- a/target/i386/whpx/whpx-all.c > +++ b/target/i386/whpx/whpx-all.c > @@ -1471,14 +1471,14 @@ static void whpx_vcpu_pre_run(CPUState *cpu) > if (!vcpu->interruption_pending && > cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); > vcpu->interruptable = false; > new_int.InterruptionType = WHvX64PendingNmi; > new_int.InterruptionPending = 1; > new_int.InterruptionVector = 2; > } > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); > } > } > > @@ -1502,7 +1502,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) > vcpu->interruptable && (env->eflags & IF_MASK)) { > assert(!new_int.InterruptionPending); > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); > irq = cpu_get_pic_interrupt(env); > if (irq >= 0) { > new_int.InterruptionType = WHvX64PendingInterrupt; > @@ -1520,7 +1520,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) > } > } else if (vcpu->ready_for_pic_interrupt && > cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); > irq = cpu_get_pic_interrupt(env); > if (irq >= 0) { > reg_names[reg_count] = WHvRegisterPendingEvent; > @@ -1607,7 +1607,7 @@ static void whpx_vcpu_process_async_events(CPUState *cpu) > } > > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); > apic_poll_irq(x86_cpu->apic_state); > } > > @@ -1623,7 +1623,7 @@ static void whpx_vcpu_process_async_events(CPUState *cpu) > } > > if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { > - cpu->interrupt_request &= ~CPU_INTERRUPT_TPR; > + cpu_reset_interrupt(cpu, CPU_INTERRUPT_TPR); > whpx_cpu_synchronize_state(cpu); > apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, > env->tpr_access_type); > diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c > index d96b41a01c2..b091a9c6685 100644 > --- a/target/openrisc/sys_helper.c > +++ b/target/openrisc/sys_helper.c > @@ -196,7 +196,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) > env->ttmr = (rb & ~TTMR_IP) | ip; > } else { /* Clear IP bit. */ > env->ttmr = rb & ~TTMR_IP; > - cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER); > } > cpu_openrisc_timer_update(cpu); > bql_unlock(); > diff --git a/target/rx/helper.c b/target/rx/helper.c > index ce003af4219..41c9606fd1d 100644 > --- a/target/rx/helper.c > +++ b/target/rx/helper.c > @@ -63,7 +63,7 @@ void rx_cpu_do_interrupt(CPUState *cs) > env->bpsw = save_psw; > env->pc = env->fintv; > env->psw_ipl = 15; > - cs->interrupt_request &= ~CPU_INTERRUPT_FIR; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); > qemu_set_irq(env->ack, env->ack_irq); > qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); > } else if (do_irq & CPU_INTERRUPT_HARD) { > @@ -73,7 +73,7 @@ void rx_cpu_do_interrupt(CPUState *cs) > cpu_stl_data(env, env->isp, env->pc); > env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4); > env->psw_ipl = env->ack_ipl; > - cs->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > qemu_set_irq(env->ack, env->ack_irq); > qemu_log_mask(CPU_LOG_INT, > "interrupt 0x%02x raised\n", env->ack_irq); > diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c > index e4c75d0ce01..4c7faeee82b 100644 > --- a/target/s390x/tcg/excp_helper.c > +++ b/target/s390x/tcg/excp_helper.c > @@ -559,7 +559,7 @@ try_deliver: > > /* we might still have pending interrupts, but not deliverable */ > if (!env->pending_int && !qemu_s390_flic_has_any(flic)) { > - cs->interrupt_request &= ~CPU_INTERRUPT_HARD; > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > } > > /* WAIT PSW during interrupt injection or STOP interrupt */