From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
philmd@linaro.org, matheus.bernardino@oss.qualcomm.com,
ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com,
ltaylorsimpson@gmail.com, alex.bennee@linaro.org,
quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com
Subject: [PATCH v2 00/40] hexagon system emulation v2, part 1/3
Date: Mon, 1 Sep 2025 20:46:35 -0700 [thread overview]
Message-ID: <20250902034715.1947718-1-brian.cain@oss.qualcomm.com> (raw)
Several review issues have been addressed and the series is now rebased.
We are now modeling the global system register state as its own object, and
will likely want to follow up in v3 with a similar change for the global
TLB state.
Issues not yet addressed by v2 (will work on this for v3):
* "Add TCG values for sreg, greg" - combined patch
* "Add imported macro, attr defs for sysemu" - excess attributes
* "Add new macro definitions for sysemu" - READ,WRITE_SREG. Are they needed?
* "Add sysemu TCG overrides" - arch_get_system_reg() as static inline
* "Add gdb support for sys regs" - checks / mutability of regs via gdbstub TBD
* "Add initial MMU model" - hex_dump_mmu_entry, cpu_index
Brian Cain (40):
docs: Add hexagon sysemu docs
docs/system: Add hexagon CPU emulation
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
target/hexagon: Handle system/guest registers in gen_analyze_funcs.py
and hex_common.py
target/hexagon: Make gen_exception_end_tb non-static
target/hexagon: Switch to tag_ignore(), generate via
get_{user,sys}_tags()
target/hexagon: Add system event, cause codes
target/hexagon: Add privilege check, use tag_ignore()
target/hexagon: Add memory order definition
target/hexagon: Add a placeholder fp exception
target/hexagon: Add guest, system reg number defs
target/hexagon: Add guest, system reg number state
target/hexagon: Add TCG values for sreg, greg
target/hexagon: Add guest/sys reg writes to DisasContext
target/hexagon: Add imported macro, attr defs for sysemu
target/hexagon: Define DCache states
target/hexagon: Add new macro definitions for sysemu
target/hexagon: Add handlers for guest/sysreg r/w
target/hexagon: Add placeholder greg/sreg r/w helpers
target/hexagon: Add vmstate representation
target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()
target/hexagon: Define register fields for system regs
target/hexagon: Implement do_raise_exception()
target/hexagon: Add system reg insns
target/hexagon: Add sysemu TCG overrides
target/hexagon: Add implicit attributes to sysemu macros
target/hexagon: Add TCG overrides for int handler insts
target/hexagon: Add TCG overrides for thread ctl
target/hexagon: Add TCG overrides for rte, nmi
target/hexagon: Add sreg_{read,write} helpers
target/hexagon: Add locks, id, next_PC to state
target/hexagon: Add a TLB count property
target/hexagon: Add {TLB,k0}lock, cause code, wait_next_pc
target/hexagon: Add stubs for modify_ssr/get_exe_mode
target/hexagon: Add gdb support for sys regs
target/hexagon: Add initial MMU model
target/hexagon: Add clear_wait_mode() definition
target/hexagon: Define f{S,G}ET_FIELD macros
target/hexagon: Add hex_interrupts support
MAINTAINERS | 3 +
docs/devel/hexagon-sys.rst | 112 +++++
docs/devel/index-internals.rst | 1 +
docs/system/hexagon/cdsp.rst | 12 +
docs/system/hexagon/emulation.rst | 18 +
docs/system/target-hexagon.rst | 103 +++++
docs/system/targets.rst | 1 +
target/hexagon/cpu-param.h | 9 +
target/hexagon/cpu.h | 76 +++-
target/hexagon/cpu_bits.h | 87 +++-
target/hexagon/cpu_helper.h | 43 ++
target/hexagon/gen_tcg.h | 9 +
target/hexagon/gen_tcg_sys.h | 103 +++++
target/hexagon/helper.h | 23 +
target/hexagon/hex_interrupts.h | 15 +
target/hexagon/hex_mmu.h | 30 ++
target/hexagon/hex_regs.h | 115 +++++
target/hexagon/internal.h | 21 +
target/hexagon/macros.h | 40 +-
target/hexagon/sys_macros.h | 238 ++++++++++
target/hexagon/translate.h | 43 ++
target/hexagon/attribs_def.h.inc | 413 ++++++++++++++++--
target/hexagon/reg_fields_def.h.inc | 96 ++++
linux-user/hexagon/cpu_loop.c | 16 +
target/hexagon/arch.c | 5 +
target/hexagon/cpu.c | 84 +++-
target/hexagon/cpu_helper.c | 96 ++++
target/hexagon/gdbstub.c | 45 ++
target/hexagon/genptr.c | 142 ++++++
target/hexagon/hex_interrupts.c | 327 ++++++++++++++
target/hexagon/hex_mmu.c | 525 ++++++++++++++++++++++
target/hexagon/machine.c | 63 +++
target/hexagon/op_helper.c | 292 +++++++++++++
target/hexagon/translate.c | 21 +-
gdb-xml/hexagon-sys.xml | 116 +++++
target/hexagon/gen_analyze_funcs.py | 21 +-
target/hexagon/gen_helper_funcs.py | 23 +-
target/hexagon/gen_helper_protos.py | 23 +-
target/hexagon/gen_idef_parser_funcs.py | 2 +
target/hexagon/gen_op_attribs.py | 2 +-
target/hexagon/gen_opcodes_def.py | 5 +-
target/hexagon/gen_tcg_func_table.py | 14 +-
target/hexagon/gen_tcg_funcs.py | 32 +-
target/hexagon/hex_common.py | 191 +++++++-
target/hexagon/imported/encode_pp.def | 213 ++++++---
target/hexagon/imported/macros.def | 558 ++++++++++++++++++++++++
target/hexagon/imported/system.idef | 262 ++++++++++-
target/hexagon/meson.build | 14 +-
48 files changed, 4506 insertions(+), 197 deletions(-)
create mode 100644 docs/devel/hexagon-sys.rst
create mode 100644 docs/system/hexagon/cdsp.rst
create mode 100644 docs/system/hexagon/emulation.rst
create mode 100644 docs/system/target-hexagon.rst
create mode 100644 target/hexagon/cpu_helper.h
create mode 100644 target/hexagon/gen_tcg_sys.h
create mode 100644 target/hexagon/hex_interrupts.h
create mode 100644 target/hexagon/hex_mmu.h
create mode 100644 target/hexagon/sys_macros.h
create mode 100644 target/hexagon/cpu_helper.c
create mode 100644 target/hexagon/hex_interrupts.c
create mode 100644 target/hexagon/hex_mmu.c
create mode 100644 target/hexagon/machine.c
create mode 100644 gdb-xml/hexagon-sys.xml
mode change 100755 => 100644 target/hexagon/imported/macros.def
--
2.34.1
next reply other threads:[~2025-09-02 3:49 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 3:46 Brian Cain [this message]
2025-09-02 3:46 ` [PATCH v2 01/40] docs: Add hexagon sysemu docs Brian Cain
2025-09-02 3:46 ` [PATCH v2 02/40] docs/system: Add hexagon CPU emulation Brian Cain
2025-09-02 3:46 ` [PATCH v2 03/40] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2025-09-02 3:46 ` [PATCH v2 04/40] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2025-09-02 3:46 ` [PATCH v2 05/40] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2025-09-02 3:46 ` [PATCH v2 06/40] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2025-09-02 3:46 ` [PATCH v2 07/40] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via
2025-09-02 3:46 ` [PATCH v2 08/40] target/hexagon: Add system event, cause codes Brian Cain
2025-09-02 3:46 ` [PATCH v2 09/40] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2025-09-02 3:46 ` [PATCH v2 10/40] target/hexagon: Add memory order definition Brian Cain
2025-09-02 3:46 ` [PATCH v2 11/40] target/hexagon: Add a placeholder fp exception Brian Cain
2025-09-02 3:46 ` [PATCH v2 12/40] target/hexagon: Add guest, system reg number defs Brian Cain
2025-09-02 3:46 ` [PATCH v2 13/40] target/hexagon: Add guest, system reg number state Brian Cain
2025-09-02 3:46 ` [PATCH v2 14/40] target/hexagon: Add TCG values for sreg, greg Brian Cain
2025-09-02 3:46 ` [PATCH v2 15/40] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2025-09-02 3:46 ` [PATCH v2 16/40] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2025-09-02 3:46 ` [PATCH v2 17/40] target/hexagon: Define DCache states Brian Cain
2025-09-02 3:46 ` [PATCH v2 18/40] target/hexagon: Add new macro definitions for sysemu Brian Cain
2025-09-02 3:46 ` [PATCH v2 19/40] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2025-09-02 3:46 ` [PATCH v2 20/40] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2025-09-02 3:46 ` [PATCH v2 21/40] target/hexagon: Add vmstate representation Brian Cain
2025-09-02 3:46 ` [PATCH v2 22/40] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2025-09-02 3:46 ` [PATCH v2 23/40] target/hexagon: Define register fields for system regs Brian Cain
2025-09-02 3:46 ` [PATCH v2 24/40] target/hexagon: Implement do_raise_exception() Brian Cain
2025-09-02 3:47 ` [PATCH v2 25/40] target/hexagon: Add system reg insns Brian Cain
2025-09-02 3:47 ` [PATCH v2 26/40] target/hexagon: Add sysemu TCG overrides Brian Cain
2025-09-02 3:47 ` [PATCH v2 27/40] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2025-09-02 3:47 ` [PATCH v2 28/40] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2025-09-02 3:47 ` [PATCH v2 29/40] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2025-09-02 3:47 ` [PATCH v2 30/40] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2025-09-02 3:47 ` [PATCH v2 31/40] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2025-09-02 3:47 ` [PATCH v2 32/40] target/hexagon: Add locks, id, next_PC to state Brian Cain
2025-09-02 3:47 ` [PATCH v2 33/40] target/hexagon: Add a TLB count property Brian Cain
2025-09-02 3:47 ` [PATCH v2 34/40] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc Brian Cain via
2025-09-02 3:47 ` [PATCH v2 35/40] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2025-09-02 3:47 ` [PATCH v2 36/40] target/hexagon: Add gdb support for sys regs Brian Cain
2025-09-02 3:47 ` [PATCH v2 37/40] target/hexagon: Add initial MMU model Brian Cain
2025-09-02 3:47 ` [PATCH v2 38/40] target/hexagon: Add clear_wait_mode() definition Brian Cain
2025-09-02 3:47 ` [PATCH v2 39/40] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2025-09-02 3:47 ` [PATCH v2 40/40] target/hexagon: Add hex_interrupts support Brian Cain
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