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From: Brian Cain via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
	philmd@linaro.org, matheus.bernardino@oss.qualcomm.com,
	ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com,
	ltaylorsimpson@gmail.com, alex.bennee@linaro.org,
	quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com,
	Brian Cain <bcain@quicinc.com>
Subject: [PATCH v2 34/40] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc
Date: Mon,  1 Sep 2025 20:47:09 -0700	[thread overview]
Message-ID: <20250902034715.1947718-35-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250902034715.1947718-1-brian.cain@oss.qualcomm.com>

From: Brian Cain <bcain@quicinc.com>

{TLB,k0}lock counts are used to represent the TLB, k0 locks among
hardware threads.

wait_next_pc represents the program counter to set when resuming from
a wait-for-interrupts state.

cause_code contains the precise exception cause.This will be used by
subsequent commits.

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu.h     | 3 +++
 target/hexagon/cpu.c     | 4 ++++
 target/hexagon/machine.c | 4 ++++
 3 files changed, 11 insertions(+)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 8b1ff23c01..6b49912c08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -130,11 +130,14 @@ typedef struct CPUArchState {
     target_ulong t_sreg[NUM_SREGS];
 
     target_ulong greg[NUM_GREGS];
+    target_ulong wait_next_pc;
 
     /* This alias of CPUState.cpu_index is used by imported sources: */
     target_ulong threadId;
     hex_lock_state_t tlb_lock_state;
     hex_lock_state_t k0_lock_state;
+    target_ulong tlb_lock_count;
+    target_ulong k0_lock_count;
 #endif
     target_ulong next_PC;
     target_ulong new_value_usr;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 56098b4c55..43fd13cd0d 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -307,7 +307,11 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
     env->threadId = cs->cpu_index;
     env->tlb_lock_state = HEX_LOCK_UNLOCKED;
     env->k0_lock_state = HEX_LOCK_UNLOCKED;
+    env->tlb_lock_count = 0;
+    env->k0_lock_count = 0;
     env->next_PC = 0;
+    env->wait_next_pc = 0;
+    env->cause_code = HEX_EVENT_NONE;
 #endif
     env->cause_code = HEX_EVENT_NONE;
 }
diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c
index 18c3f87188..10e0fe9688 100644
--- a/target/hexagon/machine.c
+++ b/target/hexagon/machine.c
@@ -22,7 +22,11 @@ const VMStateDescription vmstate_hexagon_cpu = {
         VMSTATE_UINTTL(env.next_PC, HexagonCPU),
         VMSTATE_UINTTL(env.tlb_lock_state, HexagonCPU),
         VMSTATE_UINTTL(env.k0_lock_state, HexagonCPU),
+        VMSTATE_UINTTL(env.tlb_lock_count, HexagonCPU),
+        VMSTATE_UINTTL(env.k0_lock_count, HexagonCPU),
         VMSTATE_UINTTL(env.threadId, HexagonCPU),
+        VMSTATE_UINTTL(env.cause_code, HexagonCPU),
+        VMSTATE_UINTTL(env.wait_next_pc, HexagonCPU),
         VMSTATE_END_OF_LIST()
     },
 };
-- 
2.34.1



  parent reply	other threads:[~2025-09-02  3:49 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-02  3:46 [PATCH v2 00/40] hexagon system emulation v2, part 1/3 Brian Cain
2025-09-02  3:46 ` [PATCH v2 01/40] docs: Add hexagon sysemu docs Brian Cain
2025-09-02  3:46 ` [PATCH v2 02/40] docs/system: Add hexagon CPU emulation Brian Cain
2025-09-02  3:46 ` [PATCH v2 03/40] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2025-09-02  3:46 ` [PATCH v2 04/40] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2025-09-02  3:46 ` [PATCH v2 05/40] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2025-09-02  3:46 ` [PATCH v2 06/40] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2025-09-02  3:46 ` [PATCH v2 07/40] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via
2025-09-02  3:46 ` [PATCH v2 08/40] target/hexagon: Add system event, cause codes Brian Cain
2025-09-02  3:46 ` [PATCH v2 09/40] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2025-09-02  3:46 ` [PATCH v2 10/40] target/hexagon: Add memory order definition Brian Cain
2025-09-02  3:46 ` [PATCH v2 11/40] target/hexagon: Add a placeholder fp exception Brian Cain
2025-09-02  3:46 ` [PATCH v2 12/40] target/hexagon: Add guest, system reg number defs Brian Cain
2025-09-02  3:46 ` [PATCH v2 13/40] target/hexagon: Add guest, system reg number state Brian Cain
2025-09-02  3:46 ` [PATCH v2 14/40] target/hexagon: Add TCG values for sreg, greg Brian Cain
2025-09-02  3:46 ` [PATCH v2 15/40] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2025-09-02  3:46 ` [PATCH v2 16/40] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2025-09-02  3:46 ` [PATCH v2 17/40] target/hexagon: Define DCache states Brian Cain
2025-09-02  3:46 ` [PATCH v2 18/40] target/hexagon: Add new macro definitions for sysemu Brian Cain
2025-09-02  3:46 ` [PATCH v2 19/40] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2025-09-02  3:46 ` [PATCH v2 20/40] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2025-09-02  3:46 ` [PATCH v2 21/40] target/hexagon: Add vmstate representation Brian Cain
2025-09-02  3:46 ` [PATCH v2 22/40] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2025-09-02  3:46 ` [PATCH v2 23/40] target/hexagon: Define register fields for system regs Brian Cain
2025-09-02  3:46 ` [PATCH v2 24/40] target/hexagon: Implement do_raise_exception() Brian Cain
2025-09-02  3:47 ` [PATCH v2 25/40] target/hexagon: Add system reg insns Brian Cain
2025-09-02  3:47 ` [PATCH v2 26/40] target/hexagon: Add sysemu TCG overrides Brian Cain
2025-09-02  3:47 ` [PATCH v2 27/40] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2025-09-02  3:47 ` [PATCH v2 28/40] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2025-09-02  3:47 ` [PATCH v2 29/40] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2025-09-02  3:47 ` [PATCH v2 30/40] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2025-09-02  3:47 ` [PATCH v2 31/40] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2025-09-02  3:47 ` [PATCH v2 32/40] target/hexagon: Add locks, id, next_PC to state Brian Cain
2025-09-02  3:47 ` [PATCH v2 33/40] target/hexagon: Add a TLB count property Brian Cain
2025-09-02  3:47 ` Brian Cain via [this message]
2025-09-02  3:47 ` [PATCH v2 35/40] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2025-09-02  3:47 ` [PATCH v2 36/40] target/hexagon: Add gdb support for sys regs Brian Cain
2025-09-02  3:47 ` [PATCH v2 37/40] target/hexagon: Add initial MMU model Brian Cain
2025-09-02  3:47 ` [PATCH v2 38/40] target/hexagon: Add clear_wait_mode() definition Brian Cain
2025-09-02  3:47 ` [PATCH v2 39/40] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2025-09-02  3:47 ` [PATCH v2 40/40] target/hexagon: Add hex_interrupts support Brian Cain

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