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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
	philmd@linaro.org, matheus.bernardino@oss.qualcomm.com,
	ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com,
	ltaylorsimpson@gmail.com, alex.bennee@linaro.org,
	quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com,
	Brian Cain <bcain@quicinc.com>
Subject: [PATCH v2 06/40] target/hexagon: Make gen_exception_end_tb non-static
Date: Mon,  1 Sep 2025 20:46:41 -0700	[thread overview]
Message-ID: <20250902034715.1947718-7-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250902034715.1947718-1-brian.cain@oss.qualcomm.com>

From: Brian Cain <bcain@quicinc.com>

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/translate.h | 2 ++
 target/hexagon/translate.c | 9 ++++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index d251e2233f..2bd125297a 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -281,6 +281,8 @@ extern TCGv hex_vstore_addr[VSTORES_MAX];
 extern TCGv hex_vstore_size[VSTORES_MAX];
 extern TCGv hex_vstore_pending[VSTORES_MAX];
 
+void hex_gen_exception_end_tb(DisasContext *ctx, int excp);
+
 void process_store(DisasContext *ctx, int slot_num);
 
 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX,       0, 2)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 02fd40c160..15f5adc400 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -185,13 +185,12 @@ static void gen_end_tb(DisasContext *ctx)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception_end_tb(DisasContext *ctx, int excp)
+void hex_gen_exception_end_tb(DisasContext *ctx, int excp)
 {
     gen_exec_counters(ctx);
     tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC);
     gen_exception_raw(excp);
     ctx->base.is_jmp = DISAS_NORETURN;
-
 }
 
 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
@@ -558,7 +557,7 @@ static void gen_insn(DisasContext *ctx)
         ctx->insn->generate(ctx);
         mark_store_width(ctx);
     } else {
-        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
+        hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
     }
 }
 
@@ -912,7 +911,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
 
     nwords = read_packet_words(env, ctx, words);
     if (!nwords) {
-        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
+        hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
         return;
     }
 
@@ -927,7 +926,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
         gen_commit_packet(ctx);
         ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
     } else {
-        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
+        hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
     }
 }
 
-- 
2.34.1



  parent reply	other threads:[~2025-09-02  3:49 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-02  3:46 [PATCH v2 00/40] hexagon system emulation v2, part 1/3 Brian Cain
2025-09-02  3:46 ` [PATCH v2 01/40] docs: Add hexagon sysemu docs Brian Cain
2025-09-02  3:46 ` [PATCH v2 02/40] docs/system: Add hexagon CPU emulation Brian Cain
2025-09-02  3:46 ` [PATCH v2 03/40] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2025-09-02  3:46 ` [PATCH v2 04/40] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2025-09-02  3:46 ` [PATCH v2 05/40] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2025-09-02  3:46 ` Brian Cain [this message]
2025-09-02  3:46 ` [PATCH v2 07/40] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via
2025-09-02  3:46 ` [PATCH v2 08/40] target/hexagon: Add system event, cause codes Brian Cain
2025-09-02  3:46 ` [PATCH v2 09/40] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2025-09-02  3:46 ` [PATCH v2 10/40] target/hexagon: Add memory order definition Brian Cain
2025-09-02  3:46 ` [PATCH v2 11/40] target/hexagon: Add a placeholder fp exception Brian Cain
2025-09-02  3:46 ` [PATCH v2 12/40] target/hexagon: Add guest, system reg number defs Brian Cain
2025-09-02  3:46 ` [PATCH v2 13/40] target/hexagon: Add guest, system reg number state Brian Cain
2025-09-02  3:46 ` [PATCH v2 14/40] target/hexagon: Add TCG values for sreg, greg Brian Cain
2025-09-02  3:46 ` [PATCH v2 15/40] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2025-09-02  3:46 ` [PATCH v2 16/40] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2025-09-02  3:46 ` [PATCH v2 17/40] target/hexagon: Define DCache states Brian Cain
2025-09-02  3:46 ` [PATCH v2 18/40] target/hexagon: Add new macro definitions for sysemu Brian Cain
2025-09-02  3:46 ` [PATCH v2 19/40] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2025-09-02  3:46 ` [PATCH v2 20/40] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2025-09-02  3:46 ` [PATCH v2 21/40] target/hexagon: Add vmstate representation Brian Cain
2025-09-02  3:46 ` [PATCH v2 22/40] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2025-09-02  3:46 ` [PATCH v2 23/40] target/hexagon: Define register fields for system regs Brian Cain
2025-09-02  3:46 ` [PATCH v2 24/40] target/hexagon: Implement do_raise_exception() Brian Cain
2025-09-02  3:47 ` [PATCH v2 25/40] target/hexagon: Add system reg insns Brian Cain
2025-09-02  3:47 ` [PATCH v2 26/40] target/hexagon: Add sysemu TCG overrides Brian Cain
2025-09-02  3:47 ` [PATCH v2 27/40] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2025-09-02  3:47 ` [PATCH v2 28/40] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2025-09-02  3:47 ` [PATCH v2 29/40] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2025-09-02  3:47 ` [PATCH v2 30/40] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2025-09-02  3:47 ` [PATCH v2 31/40] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2025-09-02  3:47 ` [PATCH v2 32/40] target/hexagon: Add locks, id, next_PC to state Brian Cain
2025-09-02  3:47 ` [PATCH v2 33/40] target/hexagon: Add a TLB count property Brian Cain
2025-09-02  3:47 ` [PATCH v2 34/40] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc Brian Cain via
2025-09-02  3:47 ` [PATCH v2 35/40] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2025-09-02  3:47 ` [PATCH v2 36/40] target/hexagon: Add gdb support for sys regs Brian Cain
2025-09-02  3:47 ` [PATCH v2 37/40] target/hexagon: Add initial MMU model Brian Cain
2025-09-02  3:47 ` [PATCH v2 38/40] target/hexagon: Add clear_wait_mode() definition Brian Cain
2025-09-02  3:47 ` [PATCH v2 39/40] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2025-09-02  3:47 ` [PATCH v2 40/40] target/hexagon: Add hex_interrupts support Brian Cain

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