From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
philmd@linaro.org, matheus.bernardino@oss.qualcomm.com,
ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com,
ltaylorsimpson@gmail.com, alex.bennee@linaro.org,
quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com
Subject: [PATCH v2 09/11] tests/qtest: Add hexagon boot-serial-test
Date: Mon, 1 Sep 2025 20:49:49 -0700 [thread overview]
Message-ID: <20250902034951.1948194-10-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250902034951.1948194-1-brian.cain@oss.qualcomm.com>
Add boot-serial-test support for Hexagon architecture using the virt
machine.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
tests/qtest/boot-serial-test.c | 8 ++++++++
tests/qtest/meson.build | 2 ++
2 files changed, 10 insertions(+)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index a05d26ee99..733e0f855c 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -142,6 +142,13 @@ static const uint8_t kernel_stm32vldiscovery[] = {
0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */
};
+static const uint8_t bios_hexagon[] = {
+ 0x00, 0x40, 0x00, 0x01, /* immext(#0x10000000) */
+ 0x00, 0xc0, 0x00, 0x78, /* r0 = ##0x10000000 */
+ 0x54, 0xc0, 0x00, 0x3c, /* memb(r0+#0) = #0x54 Write 'T' */
+ 0xf8, 0xff, 0xff, 0x59 /* jump 0x0 ; Loop back to start */
+};
+
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@@ -194,6 +201,7 @@ static const testdef_t tests[] = {
{ "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
{ "arm", "stm32vldiscovery", "", "T",
sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
+ { "hexagon", "virt", "", "TT", sizeof(bios_hexagon), NULL, bios_hexagon },
{ NULL }
};
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 669d07c06b..4e79cd0a8f 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -284,6 +284,8 @@ qtests_riscv32 = \
qtests_riscv64 = ['riscv-csr-test'] + \
(unpack_edk2_blobs ? ['bios-tables-test'] : [])
+qtests_hexagon = ['boot-serial-test']
+
qos_test_ss = ss.source_set()
qos_test_ss.add(
'ac97-test.c',
--
2.34.1
next prev parent reply other threads:[~2025-09-02 3:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 3:49 [PATCH v2 00/11] hexagon system emulation v2, part 3/3 Brian Cain
2025-09-02 3:49 ` [PATCH v2 01/11] hw/hexagon: Add globalreg model Brian Cain
2025-09-02 3:49 ` [PATCH v2 02/11] hw/hexagon: Add global register tracing Brian Cain
2025-10-02 5:42 ` Philippe Mathieu-Daudé
2025-09-02 3:49 ` [PATCH v2 03/11] hw/hexagon: Add machine configs for sysemu Brian Cain
2025-09-02 3:49 ` [PATCH v2 04/11] hw/hexagon: Add v68, sa8775-cdsp0 defs Brian Cain
2025-09-02 3:49 ` [PATCH v2 05/11] hw/hexagon: Add support for cfgbase Brian Cain
2025-09-02 3:49 ` [PATCH v2 06/11] hw/hexagon: Modify "Standalone" symbols Brian Cain
2025-09-02 3:49 ` [PATCH v2 07/11] target/hexagon: add build config for softmmu Brian Cain
2025-09-02 3:49 ` [PATCH v2 08/11] hw/hexagon: Define hexagon "virt" machine Brian Cain
2025-09-02 3:49 ` Brian Cain [this message]
2025-09-02 3:49 ` [PATCH v2 10/11] hw/timer: Add QTimer device Brian Cain
2025-09-02 3:49 ` [PATCH v2 11/11] hw/intc: Add l2vic interrupt controller Brian Cain
2025-09-02 8:11 ` [PATCH v2 00/11] hexagon system emulation v2, part 3/3 Philippe Mathieu-Daudé
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