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Fri, 05 Sep 2025 00:50:21 -0700 (PDT) From: Nicholas Piggin To: qemu-riscv@nongnu.org Cc: Nicholas Piggin , Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org Subject: [PATCH v2 0/3] target/riscv: corner case fixes Date: Fri, 5 Sep 2025 17:49:55 +1000 Message-ID: <20250905074959.426911-1-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Changes: v1->v2: * Added a tcg tests build-time check for vector intrinsics support in target compiler before building new tests that require it. ci images may not support these yet unfortunately, but upgrading those will be a separate effort. There is ongoing effort to run generated test verification on the QEMU riscv CPU which has turned out a few corner cases. I added some fixes for these, as well as tcg tests. The interrupted vector test also catches a bug in "Generate strided vector loads/stores with tcg nodes." that I referred to in the v5 thread for that series. Thanks, Nick Nicholas Piggin (3): target/riscv: Fix IALIGN check in misa write target/risvc: Fix vector whole ldst vstart check tests/tcg: Add riscv test for interrupted vector ops target/riscv/csr.c | 16 +- target/riscv/vector_helper.c | 2 + tests/tcg/riscv64/Makefile.softmmu-target | 5 + tests/tcg/riscv64/Makefile.target | 15 ++ tests/tcg/riscv64/misa-ialign.S | 88 +++++++++ tests/tcg/riscv64/test-interrupted-v.c | 208 ++++++++++++++++++++++ tests/tcg/riscv64/test-vstart-overflow.c | 75 ++++++++ 7 files changed, 406 insertions(+), 3 deletions(-) create mode 100644 tests/tcg/riscv64/misa-ialign.S create mode 100644 tests/tcg/riscv64/test-interrupted-v.c create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c -- 2.51.0