[PATCH 1/7] hw/pci-host: implement Nuvoton PCIE Root Complex stub

[Yubin Zou <yubinz@google.com>]

From: Titus Rwantare <titusr@google.com>

   create a basic device to introduce the root complex registers and
   respond to its mmio configuration accesses

Signed-off-by: Titus Rwantare <titusr@google.com>
---
 hw/pci-host/Kconfig               |   4 +
 hw/pci-host/meson.build           |   1 +
 hw/pci-host/npcm_pcierc.c         | 164 ++++++++++++++++++++++++++++++++++++++
 hw/pci-host/trace-events          |   4 +
 include/hw/pci-host/npcm_pcierc.h |  55 +++++++++++++
 5 files changed, 228 insertions(+)

diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 9824fa188d6b8865dcf7b069f2c16f269b211aa0..1d726b6e05c732b69e22aa2883892aaeaed129fa 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -108,3 +108,7 @@ config GT64120
     select PCI
     select EMPTY_SLOT
     select I8259
+
+config NPCM_PCIERC
+    bool
+    select PCI_EXPRESS
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 937a0f72acf940f963fc683ab52a5f8b80657ca3..2c0a49cbc5102110f7d92e279df1ad4654570332 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -30,6 +30,7 @@ pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c'))
 # ARM devices
 pci_ss.add(when: 'CONFIG_PCI_EXPRESS_FSL_IMX8M_PHY', if_true: files('fsl_imx8m_phy.c'))
 pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c'))
+pci_ss.add(when: 'CONFIG_NPCM_PCIERC', if_true: files('npcm_pcierc.c'))
 
 # HPPA devices
 specific_ss.add(when: 'CONFIG_ASTRO', if_true: files('astro.c'))
diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c
new file mode 100644
index 0000000000000000000000000000000000000000..3afe92e264f6ce4312e94f05b5e908840008df64
--- /dev/null
+++ b/hw/pci-host/npcm_pcierc.c
@@ -0,0 +1,164 @@
+/*
+ * Nuvoton PCIe Root complex
+ *
+ * Copyright 2022 Google LLC
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/pci-host/npcm_pcierc.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qom/object.h"
+#include "trace.h"
+
+static uint64_t npcm_pcierc_cfg_read(void *opaque, hwaddr addr, unsigned size)
+{
+    NPCMPCIERCState *s = NPCM_PCIERC(opaque);
+    uint32_t ret = -1;
+
+    switch (addr) {
+    case NPCM_PCIERC_RCCFGNUM:
+        ret = s->rccfgnum;
+        break;
+
+    case NPCM_PCIERC_INTEN:
+        ret = s->rcinten;
+        break;
+
+    case NPCM_PCIERC_INTST:
+        ret = s->rcintstat;
+        break;
+
+    case NPCM_PCIERC_IMSI_ADDR:
+        ret = s->rcimsiaddr;
+        break;
+
+    case NPCM_PCIERC_MSISTAT:
+        ret = s->rcmsisstat;
+        break;
+
+    case NPCM_PCIERC_AXI_ERROR_REPORT:
+        ret = s->axierr;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: read from unimplemented register 0x%04lx\n",
+                      __func__, addr);
+        ret = -1;
+        break;
+    }
+    trace_npcm_pcierc_read(addr, size, ret);
+    return ret;
+}
+
+static void npcm_pcierc_cfg_write(void *opaque, hwaddr addr, uint64_t data,
+                                  unsigned size)
+{
+    NPCMPCIERCState *s = NPCM_PCIERC(opaque);
+
+    trace_npcm_pcierc_write(addr, size, data);
+    switch (addr) {
+    case NPCM_PCIERC_RCCFGNUM:
+        s->rccfgnum = data;
+        break;
+
+    case NPCM_PCIERC_INTEN:
+        s->rcinten = data;
+        break;
+
+    case NPCM_PCIERC_INTST:
+        s->rcintstat &= ~data;
+        break;
+
+    case NPCM_PCIERC_IMSI_ADDR:
+        s->rcimsiaddr = data;
+        break;
+
+    case NPCM_PCIERC_MSISTAT:
+        s->rcmsisstat &= ~data;
+        break;
+
+    case NPCM_PCIERC_AXI_ERROR_REPORT:
+        s->axierr = data;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: write to unimplemented reg 0x%04lx data: 0x%lx\n",
+                      __func__, addr, data);
+        break;
+    }
+}
+
+static void npcm_pcierc_reset(Object *obj, ResetType type)
+{
+    NPCMPCIERCState *s = NPCM_PCIERC(obj);
+
+    s->rccfgnum = 0;
+    s->rcinten = 0;
+    s->rcintstat = 0;
+    s->rcimsiaddr = 0;
+    s->rcmsisstat = 0;
+    s->axierr = 0;
+}
+
+static const char *npcm_pcierc_root_bus_path(PCIHostState *host_bridge,
+                                             PCIBus *rootbus)
+{
+    return "0000:00";
+}
+
+static const MemoryRegionOps npcm_pcierc_cfg_ops = {
+    .read       = npcm_pcierc_cfg_read,
+    .write      = npcm_pcierc_cfg_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+        .unaligned = false,
+    },
+};
+
+static void npcm_pcierc_realize(DeviceState *dev, Error **errp)
+{
+    NPCMPCIERCState *s = NPCM_PCIERC(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &npcm_pcierc_cfg_ops,
+                          s, TYPE_NPCM_PCIERC, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void npcm_pcierc_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIHostBridgeClass *hbc = PCI_HOST_BRIDGE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    hbc->root_bus_path = npcm_pcierc_root_bus_path;
+    dc->realize = npcm_pcierc_realize;
+    rc->phases.enter = npcm_pcierc_reset;
+    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+    dc->fw_name = "pci";
+}
+
+static const TypeInfo npcm_pcierc_type_info = {
+    .name = TYPE_NPCM_PCIERC,
+    .parent = TYPE_PCIE_HOST_BRIDGE,
+    .instance_size = sizeof(NPCMPCIERCState),
+    .class_init = npcm_pcierc_class_init,
+};
+
+static void npcm_pcierc_register_types(void)
+{
+    type_register_static(&npcm_pcierc_type_info);
+}
+
+type_init(npcm_pcierc_register_types)
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 0a816b9aa129bb0c37d207e2612e09ac4762d51a..e4794f687177ee90fe4d33194b484c83a34dcaf9 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -69,3 +69,7 @@ elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx
 elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
 iosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64
 iosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64
+
+# npmc_pcierc.c
+npcm_pcierc_read(uint64_t offset, uint32_t size, uint64_t data) "offset: 0x%" PRIx64 " size: %d data: 0x%" PRIx64
+npcm_pcierc_write(uint64_t offset, uint32_t size, uint64_t data) "offset: 0x%" PRIx64 " size: %d data: 0x%" PRIx64
diff --git a/include/hw/pci-host/npcm_pcierc.h b/include/hw/pci-host/npcm_pcierc.h
new file mode 100644
index 0000000000000000000000000000000000000000..2c817147d495fdc1d1fa4b389bad0469fd6a825e
--- /dev/null
+++ b/include/hw/pci-host/npcm_pcierc.h
@@ -0,0 +1,55 @@
+/*
+ * Nuvoton PCIe Root complex
+ *
+ * Copyright 2022 Google LLC
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * The PCIERC configuration registers must be initialised by the BMC kernel
+ * during boot for PCIe to function
+ * - A single window from the PCIe to the Memory controller
+ * - 4 windows from the BMC to the PCIe.
+ *     1 of these five BMC-to-PCIe windows must be allocated for configuration
+ *     transactions, the rest can be used for I/0 or memory transactions
+ * - All BMC-to-PCIe windows are mapped to address range
+ *   0xe800_0000 to 0xefff_ffff (128MB)
+ */
+
+#ifndef NPCM_PCIERC_H
+#define NPCM_PCIERC_H
+
+#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pcie_host.h"
+#include "qom/object.h"
+
+/* PCIe Root Complex Registers */
+#define LINKSTAT                        0x92
+#define NPCM_PCIERC_RCCFGNUM            0x140 /* Configuration Number */
+#define NPCM_PCIERC_INTEN               0x180 /* Interrupt Enable */
+#define NPCM_PCIERC_INTST               0x184 /* Interrupt Status */
+#define NPCM_PCIERC_IMSI_ADDR           0x190
+#define NPCM_PCIERC_MSISTAT             0x194 /* MSI Status Register */
+#define NPCM_PCIERC_AXI_ERROR_REPORT    0x3E0
+
+#define TYPE_NPCM_PCIERC "npcm-pcie-root-complex"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCIERCState, NPCM_PCIERC)
+
+struct NPCMPCIERCState {
+    PCIExpressHost parent;
+
+    qemu_irq irq;
+
+    /* PCIe RC registers */
+    MemoryRegion mmio;
+    uint32_t rccfgnum;
+    uint32_t rcinten;
+    uint32_t rcintstat;
+    uint32_t rcimsiaddr;
+    uint32_t rcmsisstat;
+    uint32_t axierr;
+};
+
+#endif /* NPCM_PCIERC_H */

-- 
2.51.0.384.g4c02a37b29-goog