[PATCH 5/7] hw/pci-host: enable MSI on npcm PCIe root complex

[Yubin Zou <yubinz@google.com>]

From: Titus Rwantare <titusr@google.com>

This allows MSI capable qemu devices to attach to the root complex

Signed-off-by: Titus Rwantare <titusr@google.com>
---
 hw/pci-host/npcm_pcierc.c         | 5 +++++
 include/hw/pci-host/npcm_pcierc.h | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c
index a1767335fe79a30464acf32ae94fc14e417c89eb..0af76d1067a78bdbb169af3e3d5c4a2514cd0ff5 100644
--- a/hw/pci-host/npcm_pcierc.c
+++ b/hw/pci-host/npcm_pcierc.c
@@ -10,6 +10,7 @@
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
 #include "hw/pci-host/npcm_pcierc.h"
+#include "hw/pci/msi.h"
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "qemu/units.h"
@@ -442,6 +443,10 @@ static void npcm_pcierc_realize(DeviceState *dev, Error **errp)
     address_space_init(&s->pcie_space, &s->pcie_root, "pcie-address-space");
     pci_realize_and_unref(root, pci->bus, &error_fatal);
     pci_setup_iommu(pci->bus, &npcm_pcierc_iommu_ops, s);
+
+    msi_nonbroken = true;
+    msi_init(root, NPCM_PCIERC_MSI_OFFSET, NPCM_PCIERC_MSI_NR,
+             true, true, errp);
 }
 
 static void npcm_pcie_root_port_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/pci-host/npcm_pcierc.h b/include/hw/pci-host/npcm_pcierc.h
index a47eae0084b88ba4388681b24ab97f77a4338594..7d18177510f60d49f7fae7908dd1e3bfbe9ae12b 100644
--- a/include/hw/pci-host/npcm_pcierc.h
+++ b/include/hw/pci-host/npcm_pcierc.h
@@ -87,6 +87,8 @@
 #define NPCM_PCIERC_NUM_PA_WINDOWS          2
 #define NPCM_PCIERC_NUM_AP_WINDOWS          5
 
+#define NPCM_PCIERC_MSI_NR                  32
+#define NPCM_PCIERC_MSI_OFFSET              0x50
 /* PCIe extended config space offsets */
 #define NPCM_PCIE_HEADER_OFFSET             0x80
 #define NPCM_PCIE_AER_OFFSET                0x100

-- 
2.51.0.384.g4c02a37b29-goog