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Wed, 10 Sep 2025 09:37:19 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-88c35d4bbc5sm265997439f.27.2025.09.10.09.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 09:37:19 -0700 (PDT) Date: Wed, 10 Sep 2025 11:37:18 -0500 From: Andrew Jones To: Xie Bo Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, anup@brainfault.org, alistair.francis@wdc.com, rkrcmar@ventanamicro.com, palmer@dabbelt.com, xiamy@ultrarisc.com Subject: Re: [PATCH v6 1/2] Set KVM initial privilege mode and mp_state Message-ID: <20250910-70e85bb0410ddfa6fb425b0a@orel> References: <20250910093529.614305-1-xb@ultrarisc.com> <20250910093529.614305-2-xb@ultrarisc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250910093529.614305-2-xb@ultrarisc.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=ajones@ventanamicro.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Sep 10, 2025 at 05:35:27PM +0800, Xie Bo wrote: > For KVM mode, the privilege mode should not include M-mode, and the > initial value should be set to S-mode. Additionally, a following patch > adds the implementation of putting the vCPU privilege mode to KVM. > When the vCPU runs for the first time, QEMU will first put the privilege > state to KVM. If the initial value is set to M-mode, KVM will encounter > an error. > > In addition, this patch introduces the 'mp_state' field to RISC-V > vCPUs, following the convention used by KVM on x86. The 'mp_state' > reflects the multiprocessor state of a vCPU, and is used to control > whether the vCPU is runnable by KVM. Randomly select one CPU as the > boot CPU. > > Signed-off-by: Xie Bo > --- > target/riscv/cpu.c | 17 ++++++++++++++++- > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 09ded6829a..57b8c421bd 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -38,6 +38,7 @@ > #include "kvm/kvm_riscv.h" > #include "tcg/tcg-cpu.h" > #include "tcg/tcg.h" > +#include "hw/boards.h" > > /* RISC-V CPU definitions */ > static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; > @@ -1031,18 +1032,32 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) > #ifndef CONFIG_USER_ONLY > uint8_t iprio; > int i, irq, rdzero; > + static int boot_cpu_index = -1; > #endif > CPUState *cs = CPU(obj); > RISCVCPU *cpu = RISCV_CPU(cs); > RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); > CPURISCVState *env = &cpu->env; > + MachineState *ms = MACHINE(qdev_get_machine()); > > if (mcc->parent_phases.hold) { > mcc->parent_phases.hold(obj, type); > } > #ifndef CONFIG_USER_ONLY > env->misa_mxl = mcc->misa_mxl_max; > - env->priv = PRV_M; > + if (kvm_enabled()) { > + env->priv = PRV_S; > + } else { > + env->priv = PRV_M; > + } > + if (boot_cpu_index < 0) { > + boot_cpu_index = g_random_int() % ms->smp.cpus; I don't think we're obliged to use the same boot cpu on each reset after initially randomly selecting it. We can randomly select each time. Also, we can use g_random_int_range() instead of the mod. Thanks, drew > + } > + if (cs->cpu_index == boot_cpu_index) { > + env->mp_state = KVM_MP_STATE_RUNNABLE; > + } else { > + env->mp_state = KVM_MP_STATE_STOPPED; > + } > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > if (env->misa_mxl > MXL_RV32) { > /* > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 51e49e03de..4b1c5bf0e4 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -256,6 +256,8 @@ struct CPUArchState { > #endif > > target_ulong priv; > + /* Current multiprocessor state of this vCPU. */ > + uint32_t mp_state; > /* CSRs for execution environment configuration */ > uint64_t menvcfg; > target_ulong senvcfg; > -- > 2.43.0 >