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From: TANG Tiancheng <lyndra@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	 Alistair Francis <alistair.francis@wdc.com>,
	 Weiwei Li <liwei1518@gmail.com>,
	 Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	 Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	qemu-riscv@nongnu.org,  Peter Xu <peterx@redhat.com>,
	Fabiano Rosas <farosas@suse.de>,
	 TANG Tiancheng <lyndra@linux.alibaba.com>
Subject: [PATCH v2 4/4] target/riscv: Save stimer and vstimer in CPU vmstate
Date: Wed, 10 Sep 2025 23:04:28 +0800	[thread overview]
Message-ID: <20250910-timers-v2-4-31359f1f6ee8@linux.alibaba.com> (raw)
In-Reply-To: <20250910-timers-v2-0-31359f1f6ee8@linux.alibaba.com>

vmstate_riscv_cpu was missing env.stimer and env.vstimer.
Without migrating these QEMUTimer fields, active S/VS-mode
timer events are lost after snapshot or migration.

Add VMSTATE_TIMER_PTR() entries to save and restore them.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
---
 target/riscv/machine.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 1600ec44f0b755fdd49fc0df47c2288c9940afe0..51e0567ed30cbab5e791ea904165bc1854709192 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -400,6 +400,30 @@ static const VMStateDescription vmstate_ssp = {
     }
 };
 
+static bool sstc_timer_needed(void *opaque)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    if (!cpu->cfg.ext_sstc) {
+        return false;
+    }
+
+    return env->stimer != NULL || env->vstimer != NULL;
+}
+
+static const VMStateDescription vmstate_sstc = {
+    .name = "cpu/timer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = sstc_timer_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_TIMER_PTR(env.stimer, RISCVCPU),
+        VMSTATE_TIMER_PTR(env.vstimer, RISCVCPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 10,
@@ -476,6 +500,7 @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_elp,
         &vmstate_ssp,
         &vmstate_ctr,
+        &vmstate_sstc,
         NULL
     }
 };

-- 
2.43.0



      parent reply	other threads:[~2025-09-10 15:06 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-10 15:04 [PATCH v2 0/4] Fix RISC-V timer migration issues TANG Tiancheng
2025-09-10 15:04 ` [PATCH v2 1/4] hw/intc: Save time_delta in RISC-V mtimer VMState TANG Tiancheng
2025-09-10 15:04 ` [PATCH v2 2/4] include/migration: Add support for a variable-length array of UINT32 pointers TANG Tiancheng
2025-09-10 15:37   ` Peter Xu
2025-09-10 15:04 ` [PATCH v2 3/4] hw/intc: Save timers array in RISC-V mtimer VMState TANG Tiancheng
2025-09-10 15:04 ` TANG Tiancheng [this message]

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