* [PATCH v7 for v10.0.0 1/2] Set KVM initial privilege mode and mp_state
2025-09-11 8:36 [PATCH v7 for v10.0.0 0/2] target/riscv：Fix riscv64 kvm migration Xie Bo
@ 2025-09-11 8:36 ` Xie Bo
2025-09-11 12:46 ` Andrew Jones
2025-09-11 8:36 ` [PATCH v7 for v10.0.0 2/2] Fix VM resume after QEMU+KVM migration Xie Bo
2025-09-11 12:44 ` [PATCH v7 for v10.0.0 0/2] target/riscv：Fix riscv64 kvm migration Andrew Jones
2 siblings, 1 reply; 5+ messages in thread
From: Xie Bo @ 2025-09-11 8:36 UTC (permalink / raw)
To: qemu-devel
Cc: ajones, qemu-riscv, mjt, pbonzini, anup, alistair.francis,
rkrcmar, palmer, xiamy, Xie Bo
For KVM mode, the privilege mode should not include M-mode, and the
initial value should be set to S-mode. Additionally, a following patch
adds the implementation of putting the vCPU privilege mode to KVM.
When the vCPU runs for the first time, QEMU will first put the privilege
state to KVM. If the initial value is set to M-mode, KVM will encounter
an error.
In addition, this patch introduces the 'mp_state' field to RISC-V
vCPUs, following the convention used by KVM on x86. The 'mp_state'
reflects the multiprocessor state of a vCPU, and is used to control
whether the vCPU is runnable by KVM. Randomly select one CPU as the
boot CPU. Since each CPU executes the riscv_cpu_reset_hold() function
and CPU0 executes first, only CPU0 randomly selects the boot CPU.
Signed-off-by: Xie Bo <xb@ultrarisc.com>
---
target/riscv/cpu.c | 17 ++++++++++++++++-
target/riscv/cpu.h | 2 ++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 09ded6829a..f6c787ebdc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -38,6 +38,7 @@
#include "kvm/kvm_riscv.h"
#include "tcg/tcg-cpu.h"
#include "tcg/tcg.h"
+#include "hw/boards.h"
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
@@ -1031,18 +1032,32 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
#ifndef CONFIG_USER_ONLY
uint8_t iprio;
int i, irq, rdzero;
+ static int boot_cpu_index;
#endif
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
CPURISCVState *env = &cpu->env;
+ MachineState *ms = MACHINE(qdev_get_machine());
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj, type);
}
#ifndef CONFIG_USER_ONLY
env->misa_mxl = mcc->misa_mxl_max;
- env->priv = PRV_M;
+ if (kvm_enabled()) {
+ env->priv = PRV_S;
+ } else {
+ env->priv = PRV_M;
+ }
+ if (cs->cpu_index == 0) {
+ boot_cpu_index = g_random_int_range(0, ms->smp.cpus);
+ }
+ if (cs->cpu_index == boot_cpu_index) {
+ env->mp_state = KVM_MP_STATE_RUNNABLE;
+ } else {
+ env->mp_state = KVM_MP_STATE_STOPPED;
+ }
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51e49e03de..4b1c5bf0e4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -256,6 +256,8 @@ struct CPUArchState {
#endif
target_ulong priv;
+ /* Current multiprocessor state of this vCPU. */
+ uint32_t mp_state;
/* CSRs for execution environment configuration */
uint64_t menvcfg;
target_ulong senvcfg;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v7 for v10.0.0 2/2] Fix VM resume after QEMU+KVM migration
2025-09-11 8:36 [PATCH v7 for v10.0.0 0/2] target/riscv：Fix riscv64 kvm migration Xie Bo
2025-09-11 8:36 ` [PATCH v7 for v10.0.0 1/2] Set KVM initial privilege mode and mp_state Xie Bo
@ 2025-09-11 8:36 ` Xie Bo
2025-09-11 12:44 ` [PATCH v7 for v10.0.0 0/2] target/riscv：Fix riscv64 kvm migration Andrew Jones
2 siblings, 0 replies; 5+ messages in thread
From: Xie Bo @ 2025-09-11 8:36 UTC (permalink / raw)
To: qemu-devel
Cc: ajones, qemu-riscv, mjt, pbonzini, anup, alistair.francis,
rkrcmar, palmer, xiamy, Xie Bo
Fix two migration issues for virtual machines in KVM mode:
1.It saves and restores the vCPU's privilege mode to ensure that the
vCPU's privilege mode is correct after migration.
2.It saves and restores the vCPU's mp_state (runnable or stopped) and
includes this state in the migration sequence, upgrading the vmstate
version to ensure that the vCPU's mp_state is correct after migration.
KVM_PUT_RUNTIME_STATE only synchronizes the vCPU’s runtime-modified
state (such as registers), whereas mp_state is related to system boot,
multi-core initialization, and is not modified during normal operation.
Therefore, mp_state is only synchronized to KVM during KVM_PUT_RESET_STATE
and KVM_PUT_FULL_STATE.
Signed-off-by: Xie Bo <xb@ultrarisc.com>
---
target/riscv/kvm/kvm-cpu.c | 60 ++++++++++++++++++++++++++++--------
target/riscv/kvm/kvm_riscv.h | 3 +-
target/riscv/machine.c | 5 +--
3 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 0f4997a918..1434dd1c51 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -576,6 +576,12 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
}
env->pc = reg;
+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, mode), ®);
+ if (ret) {
+ return ret;
+ }
+ env->priv = reg;
+
for (i = 1; i < 32; i++) {
uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
ret = kvm_get_one_reg(cs, id, ®);
@@ -601,6 +607,12 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
return ret;
}
+ reg = env->priv;
+ ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, mode), ®);
+ if (ret) {
+ return ret;
+ }
+
for (i = 1; i < 32; i++) {
uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
reg = env->gpr[i];
@@ -1244,25 +1256,52 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)
return ret;
}
+ ret = kvm_riscv_sync_mpstate_to_qemu(cs);
+ if (ret) {
+ return ret;
+ }
+
return ret;
}
-int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
+int kvm_riscv_sync_mpstate_to_kvm(CPUState *cs)
{
+ int ret = 0;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
if (cap_has_mp_state) {
struct kvm_mp_state mp_state = {
- .mp_state = state
+ .mp_state = env->mp_state
};
- int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_MP_STATE, &mp_state);
if (ret) {
- fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n",
+ fprintf(stderr, "%s: failed to sync MP_STATE to KVM %d/%s\n",
__func__, ret, strerror(-ret));
- return -1;
}
}
- return 0;
+ return ret;
+}
+
+int kvm_riscv_sync_mpstate_to_qemu(CPUState *cs)
+{
+ int ret = 0;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (cap_has_mp_state) {
+ struct kvm_mp_state mp_state;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
+ if (ret) {
+ fprintf(stderr, "%s: failed to sync MP_STATE to QEMU %d/%s\n",
+ __func__, ret, strerror(-ret));
+ return ret;
+ }
+ env->mp_state = mp_state.mp_state;
+ }
+
+ return ret;
}
int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
@@ -1289,13 +1328,8 @@ int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
return ret;
}
- if (KVM_PUT_RESET_STATE == level) {
- RISCVCPU *cpu = RISCV_CPU(cs);
- if (cs->cpu_index == 0) {
- ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE);
- } else {
- ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED);
- }
+ if (level >= KVM_PUT_RESET_STATE) {
+ ret = kvm_riscv_sync_mpstate_to_kvm(cs);
if (ret) {
return ret;
}
diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
index b2bcd1041f..953db94160 100644
--- a/target/riscv/kvm/kvm_riscv.h
+++ b/target/riscv/kvm/kvm_riscv.h
@@ -28,7 +28,8 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
uint64_t aplic_base, uint64_t imsic_base,
uint64_t guest_num);
void riscv_kvm_aplic_request(void *opaque, int irq, int level);
-int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
+int kvm_riscv_sync_mpstate_to_kvm(CPUState *cs);
+int kvm_riscv_sync_mpstate_to_qemu(CPUState *cs);
void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 889e2b6570..8562a0a1d6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -401,8 +401,8 @@ static const VMStateDescription vmstate_ssp = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 10,
- .minimum_version_id = 10,
+ .version_id = 11,
+ .minimum_version_id = 11,
.post_load = riscv_cpu_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -422,6 +422,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UNUSED(4),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
+ VMSTATE_UINT32(env.mp_state, RISCVCPU),
VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
VMSTATE_UINT64(env.resetvec, RISCVCPU),
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread