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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:01:14.7309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7acafb50-56d1-4703-0fe5-08ddf1e34f61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4195 Received-SPF: permerror client-ip=2a01:111:f403:2409::62d; envelope-from=Luc.Michel@amd.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org v5: - Patch 36 (xlnx-versal-crl versal2 version): replaced `return NULL' with a `g_assert_not_reached()' in the versal2_decode_periph_rst function. [Phil] - Fixed remaining memory leaks in the Versal SoC by adding a finalize function. [Peter] - Patch 39 (cortex-a78ae addition): - Switched to the last r0p3 revision. - Removed the CBAR_RO and BACKCOMPAT_CNTFRQ features. - Fixed the comments referring to TRM sections. [Peter] v4: - Fixed compilation issues and runtime crashes in 3 intermediate patches. [Edgar] - Introduced a small hack to keep the GEM FDT node order as it was before. This is to avoid kernel iface name swapping (eth0 <-> eth1) in Versal. [Edgar] v3: - Dropped qemu_get_cpu() usage in the machine code. Added an getter on the SoC interface to retrieve the boot CPU instead. [Phil] - Cleaned the mp_affinity logic. Drop the mask attribute and assume it's always 0xff (the Affx fields in MPIDR are 8 bits long). Use the ARM_AFFx_SHIFT constant instead of hardcoded values in .mp_affinity description. [Phil] - Avocado test renaming in patch 41 instead of 47. [Phil] - Documentation tweak. [Phil] v2: - Addressed formatting/typo issues [Francisco] - Patch 23: GICv3 first-cpu-idx: addressed the KVM case by bailing out if not 0 at realize. I chose this path as I don't have a clear view of what it means to implement that for KVM. It seems to make sense anyway as this property is meant to be used for modeling of non-SMP systems. [Peter] - Patch 39: added a comment to clarify cortex-a78ae != cortex-a78 [Peter] Hello, This series brings support for the AMD Versal Gen 2 (versal2) SoC in QEMU. This SoC is the next iteration of the existing Versal SoC. It is organized as follows: - The first and biggest part of the series performs refactoring of the existing versal SoC implementation. This consists in: - splitting existing device types into base/concrete classes, - moving from an in-place to dynamic device creation approach in the SoC code for flexibility, - describing the SoC using a new structure called VersalMap, - moving the DTB creation logic in the SoC code itself alongside device creation. Patches are split such that each device is individually converted to use this new approach. Behaviour changes are minimal and are emphasised in the commit messages. This gets the SoC code ready for versal2 addition and leverage the fact that Versal family SoCs are quite similar in term of architecture. - versal2 SoC support is then added by adding the corresponding VersalMap description. This allows to reuse the existing code without duplication and almost no special case. - The amd-versal2-virt machine is finally added, following the same idea as amd-versal-virt. The documentation and tests are updated accordingly. Note that the xlnx-versal-virt machine is renamed amd-versal-virt to follow current branding guidelines and stay coherent with the new amd-versal2-virt machine. The xlnx-versal-virt name is kept as an alias to amd-versal-virt for command line backward compatibility. Thanks Luc Francisco Iglesias (1): hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel (46): hw/arm/xlnx-versal: split the xlnx-versal type hw/arm/xlnx-versal: prepare for FDT creation hw/arm/xlnx-versal: uart: refactor creation hw/arm/xlnx-versal: canfd: refactor creation hw/arm/xlnx-versal: sdhci: refactor creation hw/arm/xlnx-versal: gem: refactor creation hw/arm/xlnx-versal: adma: refactor creation hw/arm/xlnx-versal: xram: refactor creation hw/arm/xlnx-versal: usb: refactor creation hw/arm/xlnx-versal: efuse: refactor creation hw/arm/xlnx-versal: ospi: refactor creation hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation hw/arm/xlnx-versal: bbram: refactor creation hw/arm/xlnx-versal: trng: refactor creation hw/arm/xlnx-versal: rtc: refactor creation hw/arm/xlnx-versal: cfu: refactor creation hw/arm/xlnx-versal: crl: refactor creation hw/arm/xlnx-versal-virt: virtio: refactor creation hw/arm/xlnx-versal: refactor CPU cluster creation hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping hw/arm/xlnx-versal: instantiate the GIC ITS in the APU hw/arm/xlnx-versal: add support for multiple GICs hw/arm/xlnx-versal: add support for GICv2 hw/arm/xlnx-versal: rpu: refactor creation hw/arm/xlnx-versal: ocm: refactor creation hw/arm/xlnx-versal: ddr: refactor creation hw/arm/xlnx-versal: add the versal_get_num_cpu accessor hw/misc/xlnx-versal-crl: remove unnecessary include directives hw/misc/xlnx-versal-crl: split into base/concrete classes hw/misc/xlnx-versal-crl: refactor device reset logic hw/arm/xlnx-versal: reconnect the CRL to the other devices hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices hw/arm/xlnx-versal: tidy up hw/misc/xlnx-versal-crl: add the versal2 version hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap hw/arm/xlnx-versal: add the target field in IRQ descriptor target/arm/tcg/cpu64: add the cortex-a78ae CPU hw/arm/xlnx-versal: add versal2 SoC hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt hw/arm/xlnx-versal-virt: split into base/concrete classes hw/arm/xlnx-versal-virt: tidy up docs/system/arm/xlnx-versal-virt: update supported devices docs/system/arm/xlnx-versal-virt: add a note about dumpdtb hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine tests/functional/test_aarch64_xlnx_versal: test the versal2 machine docs/system/arm/xlnx-versal-virt.rst | 80 +- include/hw/arm/xlnx-versal-version.h | 16 + include/hw/arm/xlnx-versal.h | 342 +-- include/hw/intc/arm_gicv3_common.h | 1 + include/hw/misc/xlnx-versal-crl.h | 378 ++- hw/arm/xlnx-versal-virt.c | 741 ++---- hw/arm/xlnx-versal.c | 2474 +++++++++++++----- hw/intc/arm_gicv3_common.c | 3 +- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_kvm.c | 6 + hw/misc/xlnx-versal-crl.c | 602 ++++- target/arm/tcg/cpu64.c | 78 + tests/functional/aarch64/test_xlnx_versal.py | 12 +- 13 files changed, 3075 insertions(+), 1660 deletions(-) create mode 100644 include/hw/arm/xlnx-versal-version.h -- 2.50.1