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From: Luc Michel <luc.michel@amd.com>
To: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>
Cc: "Luc Michel" <luc.michel@amd.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Francisco Iglesias" <francisco.iglesias@amd.com>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Frederic Konrad" <frederic.konrad@amd.com>,
	"Sai Pavan Boddu" <sai.pavan.boddu@amd.com>
Subject: [PATCH v5 15/47] hw/arm/xlnx-versal: trng: refactor creation
Date: Fri, 12 Sep 2025 12:00:24 +0200	[thread overview]
Message-ID: <20250912100059.103997-16-luc.michel@amd.com> (raw)
In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com>

Refactor the TRNG device creation using the VersalMap structure.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
 include/hw/arm/xlnx-versal.h |  2 --
 hw/arm/xlnx-versal.c         | 18 ++++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 9adce02f8a9..bba96201d37 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -18,11 +18,10 @@
 #include "hw/or-irq.h"
 #include "hw/intc/arm_gicv3.h"
 #include "hw/rtc/xlnx-zynqmp-rtc.h"
 #include "qom/object.h"
 #include "hw/misc/xlnx-versal-crl.h"
-#include "hw/misc/xlnx-versal-trng.h"
 #include "net/can_emu.h"
 #include "hw/misc/xlnx-versal-cfu.h"
 #include "hw/misc/xlnx-versal-cframe-reg.h"
 #include "target/arm/cpu.h"
 #include "hw/arm/xlnx-versal-version.h"
@@ -81,11 +80,10 @@ struct Versal {
     } lpd;
 
     /* The Platform Management Controller subsystem.  */
     struct {
         XlnxZynqMPRTC rtc;
-        XlnxVersalTRng trng;
         XlnxVersalCFUAPB cfu_apb;
         XlnxVersalCFUFDRO cfu_fdro;
         XlnxVersalCFUSFR cfu_sfr;
         XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
         XlnxVersalCFrameBcastReg cframe_bcast;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index dcf84f722f4..5054f4146f1 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -35,10 +35,11 @@
 #include "hw/usb/xlnx-usb-subsystem.h"
 #include "hw/nvram/xlnx-versal-efuse.h"
 #include "hw/ssi/xlnx-versal-ospi.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
 #include "hw/nvram/xlnx-bbram.h"
+#include "hw/misc/xlnx-versal-trng.h"
 
 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
 #define GEM_REVISION        0x40070106
 
@@ -119,10 +120,11 @@ typedef struct VersalMap {
         int irq;
     } ospi;
 
     VersalSimplePeriphMap pmc_iou_slcr;
     VersalSimplePeriphMap bbram;
+    VersalSimplePeriphMap trng;
 } VersalMap;
 
 static const VersalMap VERSAL_MAP = {
     .uart[0] = { 0xff000000, 18 },
     .uart[1] = { 0xff010000, 19 },
@@ -162,10 +164,11 @@ static const VersalMap VERSAL_MAP = {
         .irq = 124,
     },
 
     .pmc_iou_slcr = { 0xf1060000, OR_IRQ(121, 0) },
     .bbram = { 0xf11f0000, OR_IRQ(121, 1) },
+    .trng = { 0xf1230000, 141 },
 };
 
 static const VersalMap *VERSION_TO_MAP[] = {
     [VERSAL_VER_VERSAL] = &VERSAL_MAP,
 };
@@ -778,23 +781,22 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
      */
     sysbus_connect_irq(sbd, 1,
                        qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
 }
 
-static void versal_create_trng(Versal *s, qemu_irq *pic)
+static void versal_create_trng(Versal *s, const VersalSimplePeriphMap *map)
 {
     SysBusDevice *sbd;
     MemoryRegion *mr;
 
-    object_initialize_child(OBJECT(s), "trng", &s->pmc.trng,
-                            TYPE_XLNX_VERSAL_TRNG);
-    sbd = SYS_BUS_DEVICE(&s->pmc.trng);
-    sysbus_realize(sbd, &error_fatal);
+    sbd = SYS_BUS_DEVICE(qdev_new(TYPE_XLNX_VERSAL_TRNG));
+    object_property_add_child(OBJECT(s), "trng", OBJECT(sbd));
+    sysbus_realize_and_unref(sbd, &error_abort);
 
     mr = sysbus_mmio_get_region(sbd, 0);
-    memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr);
-    sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]);
+    memory_region_add_subregion(&s->mr_ps, map->addr, mr);
+    versal_sysbus_connect_irq(s, sbd, 0, map->irq);
 }
 
 static void versal_create_xrams(Versal *s, const struct VersalXramMap *map)
 {
     SysBusDevice *sbd;
@@ -1340,14 +1342,14 @@ static void versal_realize(DeviceState *dev, Error **errp)
     qdev_connect_gpio_out_named(slcr, "ospi-mux-sel", 0,
                                 qdev_get_gpio_in_named(ospi,
                                                        "ospi-mux-sel", 0));
 
     versal_create_bbram(s, &map->bbram);
+    versal_create_trng(s, &map->trng);
 
     versal_create_pmc_apb_irq_orgate(s, pic);
     versal_create_rtc(s, pic);
-    versal_create_trng(s, pic);
     versal_create_crl(s, pic);
     versal_create_cfu(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.50.1



  parent reply	other threads:[~2025-09-12 10:06 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-12 10:00 [PATCH v5 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-12 10:00 ` [PATCH v5 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-09-12 17:07   ` Edgar E. Iglesias via
2025-09-12 10:00 ` [PATCH v5 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-09-12 17:17   ` Edgar E. Iglesias
2025-09-16  7:30     ` Luc Michel
2025-09-18  6:10       ` Edgar E. Iglesias
2025-09-25 18:45         ` Edgar E. Iglesias
2025-09-26  6:32           ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-09-12 17:22   ` Edgar E. Iglesias
2025-09-16  7:34     ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-09-12 17:31   ` Edgar E. Iglesias via
2025-09-16  7:38     ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Luc Michel
2025-09-12 10:00 ` [PATCH v5 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-09-12 10:00 ` Luc Michel [this message]
2025-09-12 10:00 ` [PATCH v5 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 19/47] hw/arm/xlnx-versal-virt: virtio: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-09-12 10:00 ` [PATCH v5 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-09-12 10:00 ` [PATCH v5 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-09-12 10:00 ` [PATCH v5 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-09-12 10:00 ` [PATCH v5 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-09-12 10:00 ` [PATCH v5 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-09-12 10:00 ` [PATCH v5 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-09-12 10:00 ` [PATCH v5 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-09-12 10:00 ` [PATCH v5 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-09-12 10:00 ` [PATCH v5 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-09-12 10:00 ` [PATCH v5 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-09-12 10:00 ` [PATCH v5 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-09-12 10:00 ` [PATCH v5 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-16 14:31   ` Peter Maydell
2025-09-12 10:00 ` [PATCH v5 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-09-12 10:00 ` [PATCH v5 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-09-12 10:00 ` [PATCH v5 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-09-12 10:00 ` [PATCH v5 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-09-12 10:00 ` [PATCH v5 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-25 15:41 ` [PATCH v5 00/47] AMD Versal Gen 2 support Peter Maydell
2025-09-25 18:38   ` Edgar E. Iglesias

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