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From: Luc Michel <luc.michel@amd.com>
To: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>
Cc: "Luc Michel" <luc.michel@amd.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Francisco Iglesias" <francisco.iglesias@amd.com>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Frederic Konrad" <frederic.konrad@amd.com>,
	"Sai Pavan Boddu" <sai.pavan.boddu@amd.com>
Subject: [PATCH v5 19/47] hw/arm/xlnx-versal-virt: virtio: refactor creation
Date: Fri, 12 Sep 2025 12:00:28 +0200	[thread overview]
Message-ID: <20250912100059.103997-20-luc.michel@amd.com> (raw)
In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com>

Refactor the creation of virtio devices. Use the accessors provided by
the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
defined in the VersalMap structure.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
 include/hw/arm/xlnx-versal.h |  3 +++
 hw/arm/xlnx-versal-virt.c    | 31 ++++++++++++-------------------
 hw/arm/xlnx-versal.c         | 26 ++++++++++++++++++++++++++
 3 files changed, 41 insertions(+), 19 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index d3ce13e69de..af47acb288f 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -100,10 +100,13 @@ void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk);
 void versal_efuse_attach_drive(Versal *s, BlockBackend *blk);
 void versal_bbram_attach_drive(Versal *s, BlockBackend *blk);
 void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
                               BlockBackend *blk);
 
+qemu_irq versal_get_reserved_irq(Versal *s, int idx, int *dtb_idx);
+hwaddr versal_get_reserved_mmio_addr(Versal *s);
+
 int versal_get_num_can(VersalVersion version);
 int versal_get_num_sdhci(VersalVersion version);
 
 /* Memory-map and IRQ definitions. Copied a subset from
  * auto-generated files.  */
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d96f3433929..b981d012558 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -269,41 +269,34 @@ static void create_virtio_regions(VersalVirt *s)
 {
     int virtio_mmio_size = 0x200;
     int i;
 
     for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
-        char *name = g_strdup_printf("virtio%d", i);
-        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
-        int irq = VERSAL_RSVD_IRQ_FIRST + i;
+        hwaddr base = versal_get_reserved_mmio_addr(&s->soc)
+            + i * virtio_mmio_size;
+        g_autofree char *node = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
+        int dtb_irq;
         MemoryRegion *mr;
         DeviceState *dev;
         qemu_irq pic_irq;
 
-        pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
+        pic_irq = versal_get_reserved_irq(&s->soc, i, &dtb_irq);
         dev = qdev_new("virtio-mmio");
-        object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
+        object_property_add_child(OBJECT(s), "virtio-mmio[*]", OBJECT(dev));
         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
         memory_region_add_subregion(&s->soc.mr_ps, base, mr);
-        g_free(name);
-    }
 
-    for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
-        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
-        int irq = VERSAL_RSVD_IRQ_FIRST + i;
-        char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
-
-        qemu_fdt_add_subnode(s->fdt, name);
-        qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
-        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
-                               GIC_FDT_IRQ_TYPE_SPI, irq,
+        qemu_fdt_add_subnode(s->fdt, node);
+        qemu_fdt_setprop(s->fdt, node, "dma-coherent", NULL, 0);
+        qemu_fdt_setprop_cells(s->fdt, node, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, dtb_irq,
                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
-        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+        qemu_fdt_setprop_sized_cells(s->fdt, node, "reg",
                                      2, base, 2, virtio_mmio_size);
-        qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
-        g_free(name);
+        qemu_fdt_setprop_string(s->fdt, node, "compatible", "virtio,mmio");
     }
 }
 
 static void bbram_attach_drive(VersalVirt *s)
 {
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index e1f93dbb09c..1e4229c7670 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -152,10 +152,17 @@ typedef struct VersalMap {
             uint32_t blktype_frames[7];
         } cframe_cfg[15];
     } cfu;
 
     VersalSimplePeriphMap crl;
+
+    /* reserved MMIO/IRQ space that can safely be used for virtio devices */
+    struct VersalReserved {
+        uint64_t mmio_start;
+        int irq_start;
+        int irq_num;
+    } reserved;
 } VersalMap;
 
 static const VersalMap VERSAL_MAP = {
     .uart[0] = { 0xff000000, 18 },
     .uart[1] = { 0xff010000, 19 },
@@ -218,10 +225,12 @@ static const VersalMap VERSAL_MAP = {
             { { 38498, 3841, 15361, 13, 7, 3, 1 } },
         },
     },
 
     .crl = { 0xff5e0000, 10 },
+
+    .reserved = { 0xa0000000, 111, 8 },
 };
 
 static const VersalMap *VERSION_TO_MAP[] = {
     [VERSAL_VER_VERSAL] = &VERSAL_MAP,
 };
@@ -1424,10 +1433,27 @@ void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
 
     sysbus_connect_irq(SYS_BUS_DEVICE(ospi),
                        flash_idx + 1, cs_line);
 }
 
+qemu_irq versal_get_reserved_irq(Versal *s, int idx, int *dtb_idx)
+{
+    const VersalMap *map = versal_get_map(s);
+
+    g_assert(idx < map->reserved.irq_num);
+
+    *dtb_idx = map->reserved.irq_start + idx;
+    return versal_get_irq(s, *dtb_idx);
+}
+
+hwaddr versal_get_reserved_mmio_addr(Versal *s)
+{
+    const VersalMap *map = versal_get_map(s);
+
+    return map->reserved.mmio_start;
+}
+
 int versal_get_num_can(VersalVersion version)
 {
     const VersalMap *map = VERSION_TO_MAP[version];
 
     return map->num_canfd;
-- 
2.50.1



  parent reply	other threads:[~2025-09-12 10:04 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-12 10:00 [PATCH v5 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-12 10:00 ` [PATCH v5 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-09-12 17:07   ` Edgar E. Iglesias via
2025-09-12 10:00 ` [PATCH v5 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-09-12 17:17   ` Edgar E. Iglesias
2025-09-16  7:30     ` Luc Michel
2025-09-18  6:10       ` Edgar E. Iglesias
2025-09-25 18:45         ` Edgar E. Iglesias
2025-09-26  6:32           ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-09-12 17:22   ` Edgar E. Iglesias
2025-09-16  7:34     ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-09-12 17:31   ` Edgar E. Iglesias via
2025-09-16  7:38     ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Luc Michel
2025-09-12 10:00 ` [PATCH v5 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 15/47] hw/arm/xlnx-versal: trng: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-09-12 10:00 ` Luc Michel [this message]
2025-09-12 10:00 ` [PATCH v5 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-09-12 10:00 ` [PATCH v5 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-09-12 10:00 ` [PATCH v5 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-09-12 10:00 ` [PATCH v5 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-09-12 10:00 ` [PATCH v5 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-09-12 10:00 ` [PATCH v5 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-09-12 10:00 ` [PATCH v5 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-09-12 10:00 ` [PATCH v5 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-09-12 10:00 ` [PATCH v5 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-09-12 10:00 ` [PATCH v5 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-09-12 10:00 ` [PATCH v5 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-09-12 10:00 ` [PATCH v5 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-09-12 10:00 ` [PATCH v5 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-16 14:31   ` Peter Maydell
2025-09-12 10:00 ` [PATCH v5 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-09-12 10:00 ` [PATCH v5 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-09-12 10:00 ` [PATCH v5 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-09-12 10:00 ` [PATCH v5 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-09-12 10:00 ` [PATCH v5 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-25 15:41 ` [PATCH v5 00/47] AMD Versal Gen 2 support Peter Maydell
2025-09-25 18:38   ` Edgar E. Iglesias

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